Variable-Sized Codewords for L2P Table Storage in Volatile Memory
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Solution Overview
Problem
High-capacity storage systems face challenges in efficiently using volatile memory for logical-to-physical address table storage due to space and performance tradeoffs, leading to increased DRAM requirements and power consumption, especially in enterprise SSDs with large capacities.
Innovation Solution
The implementation of variable-sized codewords in volatile memory, such as 128+2 or 62+2 configurations, where a data payload and error correction code are used to store and update logical-to-physical address table entries, optimizing space efficiency and reducing the need for additional DRAM, along with an ASIC hardware assist to manage L2P table data within these codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fixed-size codewords are used to store L2P table entries in volatile memory, then error correction capability is maintained, but volatile memory space efficiency deteriorates and DRAM requirements increase
Solution Approach 1:
The patent applies dynamics by making the codeword size variable rather than fixed. The system dynamically adjusts the data payload size (e.g., 62 bytes or 127 bytes) while maintaining a fixed error correction code size (2 bytes), allowing optimal space utilization based on the actual number of L2P entries that need to be stored. This resolves the contradiction by enabling both error correction (through the fixed ECC portion) and space efficiency (through the variable data payload) to coexist.
Solution Approach 2:
The patent changes the parameter of codeword structure from fixed to variable. By modifying the data payload size parameter while keeping the error correction code parameter constant, the system achieves flexible memory utilization. This parameter change allows the storage system to adapt to different L2P table sizes, improving space efficiency without compromising error correction capability.
2Speed
If larger volatile memory is allocated to cache the entire L2P table, then access speed improves, but power consumption and cost increase
Solution Approach 1:
The patent applies partial action by caching only the necessary portion of the L2P table in volatile memory rather than the entire table. The variable-sized codewords allow the system to cache exactly the number of entries needed, avoiding the excessive allocation of memory resources. This partial caching strategy maintains fast access speed for active entries while reducing overall power consumption compared to caching the complete L2P table.
3Quantity of substance
If variable-sized codewords are implemented, then space efficiency improves and DRAM requirements reduce, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the volatile memory into multiple variable-sized codewords, where each codeword contains a data payload and a fixed error correction code. This segmentation allows independent management of each codeword's data portion while maintaining uniform error correction handling. The segmentation reduces overall system complexity by breaking down the large L2P table into manageable, independently addressable units.
Data Source
AI summary
A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.