Variable-Sized Mapping Units for Non-Volatile Memory
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Solution Overview
Problem
The variable-sized nature of compressed data in non-volatile memory systems, such as SSDs, complicates the mapping process due to misalignment with fixed-sized mapping unit boundaries, affecting read-modify-write operations and requiring inefficient data reduction/compression hardware operations.
Innovation Solution
Decoupling the mapping unit size from fixed restrictions allows for the aggregation of multiple logical blocks into larger variable-sized mapping units, enabling efficient mapping and reducing the size of the mapping layer by mapping logical page addresses to variable-sized pieces of data across multiple read units in non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data compression is used to reduce the size of data written to non-volatile memory, then the number of writes is reduced and space requirements are minimized, but the variable-sized nature of compressed data causes misalignment with fixed-sized mapping unit boundaries, complicating the mapping process
Solution Approach 1:
The patent segments the mapping process into two independent components: (1) a compression layer that handles variable-sized data chunks independently, and (2) a mapping layer that operates on fixed-sized units. This segmentation allows the compression layer to optimize for data reduction while the mapping layer maintains fixed boundary alignment, resolving the contradiction between reducing write operations and maintaining simple mapping processes.
Solution Approach 2:
The patent introduces an intermediary structure (the mapping layer with fixed-sized mapping units) between the compression layer (variable-sized data) and the physical storage layer. This intermediary absorbs the complexity of variable-sized data alignment and presents a simplified fixed-sized interface to the storage hardware, enabling efficient compression while maintaining straightforward mapping operations.
2Device complexity
If multiple logical blocks are aggregated into larger mapping units, then the size of the mapping layer is reduced and scalability is improved, but the mapping units become variable-sized which affects alignment with fixed hardware boundaries
Solution Approach 1:
The patent divides the storage system into distinct operational layers: the mapping layer aggregates multiple logical blocks into larger units for reduced complexity, while the compression layer handles variable-sized data independently. This segmentation allows the mapping layer to operate on variable-sized aggregated units without affecting hardware alignment, as the compression layer manages the variable boundaries.
Solution Approach 2:
The patent resolves the alignment contradiction by moving to a different dimensional perspective: instead of trying to make mapping units both large (for reduced complexity) and fixed-sized (for hardware alignment), it creates a hierarchical structure where the mapping layer operates on variable-sized aggregated units in one dimension, while the compression layer provides fixed boundary management in another dimension.
3Adaptability or versatility
If read-modify-write operations are performed on misaligned LBAs, then data can be accessed at any logical address, but the operations become inefficient and performance deteriorates
Solution Approach 1:
The patent introduces the mapping layer as an intermediary that translates any LBA request into aligned physical addresses. This intermediary handles the complexity of accessing data at any logical address while presenting aligned operations to the hardware, thereby maintaining both versatility in data accessibility and efficiency in operation execution.
Solution Approach 2:
The mapping layer performs preliminary alignment actions before data access operations occur. By pre-translating misaligned LBAs into aligned physical addresses, the system ensures that subsequent read-modify-write operations can proceed efficiently with proper alignment, resolving the contradiction between flexible address access and operational efficiency.
Data Source
AI summary
Systems and methods presented herein provide for locating data in non-volatile memory by decoupling a mapping unit size from restrictions such as the maximum size of a reducible unit to provide efficient mapping of larger mapping units. In one embodiment, a method comprises mapping a logical page address in a logical block address space to a read unit address and a number of read units in the non-volatile memory. The method also comprises mapping data of the logical page address to a plurality of variable-sized pieces of data spread across the number of read units starting at the read unit address in the non-volatile memory.