Variable Slope Ramp Signal Generation for CMOS Image Sensor Dynamic Range
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Solution Overview
Problem
Conventional CMOS image sensors face limitations in dynamic range due to the linear ramp voltage signal, leading to low picture clarity, high computational costs, and reduced frame rates when attempting to achieve high dynamic range images, particularly through multi-exposure or extended ADC bits methods.
Innovation Solution
A device and method utilizing a phase-locked loop (PLL) circuit to generate a changing ramp clock signal based on a variable signal and a reference clock, which is input to an analog-to-digital converter (ADC) circuit, allowing for a variable slope ramp signal that adapts to light conditions, thereby extending the dynamic range without increasing ramping time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-exposure technology is used to extend dynamic range, then dynamic range is improved, but picture clarity deteriorates due to camera or target shifts between exposures
Solution Approach 1:
The patent applies the Dynamics principle by implementing a variable slope ramp signal instead of a fixed linear ramp. The slope of the ramp signal dynamically adjusts during the conversion process, allowing the system to adapt to different light conditions within a single exposure. This dynamic adjustment enables the ADC to maintain high precision across the full dynamic range without requiring multiple exposures, thereby avoiding the picture clarity issues caused by camera or target shifts.
2Adaptability or versatility
If multi-exposure technology is used to extend dynamic range, then dynamic range is improved, but processing speed deteriorates due to merging multiple high resolution pictures
Solution Approach 1:
The patent applies the Preliminary action principle by performing the dynamic range extension within the ADC circuit itself through a variable slope ramp signal, rather than capturing multiple exposures and merging them later through complex software processing. The ADC circuit preemptively handles the dynamic range adaptation during the analog-to-digital conversion process, eliminating the need for subsequent computational merging operations and thus maintaining high processing speed and frame rates.
3Adaptability or versatility
If ADC bits are increased to extend dynamic range, then dynamic range is improved, but frame rate deteriorates due to increased ramping time
Solution Approach 1:
The patent applies the Parameter changes principle by changing the slope parameter of the ramp signal dynamically during the conversion process. Instead of increasing the number of ADC bits (which would require a longer ramping time and reduce frame rate), the system modifies the ramp signal's slope to optimize the conversion process. This allows the ADC to achieve extended dynamic range coverage while maintaining the original frame rate, as the ramping time remains unchanged.
4Device complexity
If linear ramp voltage signal is used, then device complexity is kept simple, but dynamic range is limited due to unchangeable LSB voltage
Solution Approach 1:
The patent applies the Dynamics principle by transitioning from a static linear ramp signal to a dynamic variable slope ramp signal. The ramp signal's slope changes during the conversion process, allowing the system to optimize performance across different portions of the dynamic range. This dynamic approach extends the effective dynamic range without requiring significant increases in device complexity, as it leverages the existing ADC architecture with a modified ramp signal generation approach.
Data Source
AI summary
A device for generating a ramp signal with a changing slope is disclosed. The device may comprise a processor configured to generate a variable signal. The device may also comprise a phase-locked loop (PLL) circuit configured to receive the variable signal and a reference clock signal, generate a changing ramp clock signal based on the variable signal and the reference clock signal, and output the generated changing ramp clock signal as an input of an analog-to-digital-converter (ADC) circuit.