Variable Spacer Vertical FETs for Leakage Reduction
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Solution Overview
Problem
In CMOS technology, scaling down MOSFETs leads to increased gate-induced drain leakage (GIDL) and gate-to-drain overlap capacitance (Cgd), which can elevate device leakage and power consumption, particularly with alternate channel materials having lower bandgaps, making it challenging to optimize source and drain overlap independently.
Innovation Solution
The method involves forming vertical field effect transistors (VFETs) with variable spacers, allowing independent modulation of source and drain overlap to the gate, achieved by creating spacers of different thicknesses on the same chip or wafer, optimizing source overlap for resistance and drain overlap for GIDL and Cgd reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If source and drain overlap are increased to reduce on-state resistance, then drive current is improved, but gate-induced drain leakage and gate-to-drain overlap capacitance increase
Solution Approach 1:
The patent applies different spacer thicknesses at different locations: a first spacer thickness at the source end and a second spacer thickness at the drain end. This local differentiation allows the source overlap to be optimized for low on-state resistance while the drain overlap is optimized to minimize GIDL and capacitance, resolving the contradiction between drive current and harmful leakage effects.
Solution Approach 2:
The gate overlap region is segmented into two distinct zones with different spacer thicknesses: a source-side overlap region and a drain-side overlap region. This segmentation enables independent optimization of each region's characteristics, allowing the source side to maximize current drive while the drain side minimizes leakage and capacitance.
2Productivity
If MOSFETs are scaled down through technology nodes, then device density is improved, but gate-induced drain leakage and gate-to-drain overlap capacitance increase
Solution Approach 1:
By implementing variable spacer thicknesses along the gate length, the patent locally optimizes the drain-side overlap region to minimize capacitance and leakage effects. This allows continued device scaling and density improvement while mitigating the harmful capacitance that typically increases with scaling.
3Power
If alternate channel materials with lower bandgaps are used, then device performance is improved, but gate-induced drain leakage increases
Solution Approach 1:
The patent compensates for the higher GIDL tendency of low-bandgap channel materials by reducing the drain-side overlap through thinner spacers in that region. This local optimization at the drain end mitigates the material-induced leakage while preserving the performance benefits of the alternate channel material.
Data Source
AI summary
A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.