Variable Span Integration Fill for Lithographic Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In advanced lithography, aligning multiple layers with different pitches in integrated circuit design becomes increasingly difficult, leading to significant spaces between structures and a loss of density, as traditional methods like using a least common multiple become impractical with more layers.
Innovation Solution
The Variable Span Integration Fill (VSIF) method allows for the placement of blocks with flexible sizing and interconnect routing, enabling alignment without strict fixed alignments, by defining anchors and targets in lithographic regions and inserting integration fill shapes to adjust spacing and meet design rule requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional alignment methods using least common multiple are used for multiple layers with different pitches, then alignment between lithographic structures is achieved, but significant spaces between structures result in loss of density
Solution Approach 1:
The patent changes the alignment parameter from fixed least common multiple spacing to variable spacing determined by diffraction pattern alignment. This allows structures to be positioned at optimal distances that maintain both alignment precision and maximum density by adjusting the spacing parameter based on the specific pitch combinations of adjacent layers.
Solution Approach 2:
The patent introduces dynamic alignment where the spacing between lithographic structures is not fixed but varies depending on the diffraction patterns of adjacent layers. This dynamic approach allows the system to adapt the spacing to achieve both precise alignment and maximum density for different layer combinations.
2Adaptability or versatility
If more layers with different pitches are added to lithographic structure, then circuit complexity and functionality are improved, but alignment difficulty increases significantly
Solution Approach 1:
The patent introduces diffraction pattern alignment as an intermediary mechanism between layers with different pitches. Instead of directly aligning structures based on their pitches, the method uses diffraction patterns as a mediator to establish alignment relationships, simplifying the alignment process for multiple layers with varying pitches.
Solution Approach 2:
The patent creates a universal alignment approach based on diffraction pattern matching that works across multiple layers with different pitches. This universal method eliminates the need for layer-specific alignment procedures, allowing the same diffraction-based alignment technique to be applied universally to any combination of layers.
3Ease of manufacture
If fixed alignment patterns are used for lithographic layers, then manufacturing process is simplified, but flexibility in block sizing and routing is reduced
Solution Approach 1:
The patent transitions from static fixed alignment patterns to dynamic diffraction-based alignment that adapts to different block sizes and routing requirements. The alignment is determined by the diffraction patterns of the actual structures being placed, allowing flexible block sizing and routing while maintaining manufacturing simplicity through an automated alignment process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
VSIF enhances manufacturability and area efficiency by allowing blocks to be integrated with different sizes and routing patterns, reducing the need for complex interface structures and minimizing space between layers, thus improving the integration of complex integrated circuits.
Implementation Method 1
diffraction of the light being used becomes a significant problem
Implementation Method 2
the diffraction pattern created by the second lithographic structure is aligned to the first lithographic structure so that no destructive interference occurs
Data Source
AI summary
Various implementations described herein are directed to a method for manufacturing an integrated circuit. The method may include defining multiple lithographic regions for the integrated circuit, and the multiple lithographic regions may include a first lithographic region and a second lithographic region. The method may include defining an anchor in the first lithographic region and defining a target in the second lithographic region. The method may include defining a spacing interval between the anchor and the target. The method may include inserting an integration fill in the spacing interval.