Variable-Thickness IC Interconnects Without Barrier Metal Layers
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Solution Overview
Problem
The existing damascene process is unable to effectively pattern metal lines and vias with different dimensions based on the performance characteristics of various circuit blocks in integrated circuits, leading to suboptimal connection performance and increased resistance/capacitance (RC) characteristics due to the use of barrier metal layers.
Innovation Solution
An interconnect structure for integrated circuits featuring metal lines divided into sections with varying thicknesses and vias with different protrusion heights and widths, where each via is a single continuous structure without a connection surface and without a barrier metal layer between the vias and the dielectric structure, allowing for customized connection to circuit blocks with different performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier metal layers are used in the damascene process to prevent material diffusion, then connection reliability is improved, but resistance/capacitance (RC) characteristics deteriorate and manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the barrier metal layer from the interconnect structure, eliminating it entirely rather than attempting to optimize its presence. This extraction resolves the contradiction by removing the source of manufacturing complexity while maintaining connection reliability through alternative design approaches.
Solution Approach 2:
The patent changes the dimensional parameters of the metal lines and vias, creating non-uniform thickness profiles and varying via dimensions to optimize electrical performance. This parameter optimization compensates for the removed barrier layer while improving RC characteristics, thereby resolving the contradiction between reliability and manufacturing complexity.
2Reliability
If barrier metal layers are used to prevent material diffusion into insulation structure, then connection reliability is improved, but RC characteristics performance decreases
Solution Approach 1:
The barrier metal layer is completely removed from the structure. This extraction eliminates the additional resistance and capacitance introduced by the barrier layer, directly improving RC characteristics while maintaining reliability through the optimized metal line and via geometry.
Solution Approach 2:
The patent optimizes the dimensional parameters of the copper metal lines and vias, creating varying thicknesses and dimensions that minimize resistance and capacitance. This parameter optimization compensates for the removed barrier layer and directly improves electrical performance by reducing energy loss.
3Ease of manufacture
If uniform metal lines and vias are used in damascene process, then manufacturing simplicity is maintained, but adaptability to different circuit block performance characteristics is reduced
Solution Approach 1:
The patent implements local quality by creating metal lines with non-uniform thickness and vias with varying dimensions at different locations. Each section of the interconnect structure is locally optimized to match the specific performance requirements of the circuit blocks it connects, thereby achieving high adaptability while maintaining manufacturing simplicity through a single process flow.
Data Source
AI summary
A interconnect structure for an integrated circuit may include: a metal line including a plurality of sections having different thicknesses along a 1st direction; and a plurality of vias respectively protruding from the plurality of sections of the metal line.