Variable-Thickness WLCSP Structure for CTE and Handling Reliability
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Solution Overview
Problem
The production of smaller sized and lower profiled Wafer Level Chip Scale Packages (WLCSPs) faces challenges in achieving high Board Level Reliability (BLR) against temperature cycling due to coefficient of thermal expansion (CTE) mismatches between the WLCSP and the PCB, and the WLCSPs are susceptible to damage from external stresses and forces during handling and shipping.
Innovation Solution
The WLCSP design incorporates critical and non-critical portions with varying thicknesses, where the critical portions are thinner to reduce CTE mismatch and the non-critical portions are thicker to enhance strength, allowing for improved handling and processing. This is achieved through semiconductor manufacturing techniques involving adhesive tapes, etching, and singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the WLCSP is made thinner to reduce profile height, then the package size is reduced, but the CTE mismatch with PCB increases causing reliability degradation
Solution Approach 1:
The patent applies local quality by creating different thickness zones within the WLCSP package. The die attach area is made thinner to reduce overall profile height, while the periphery is maintained at greater thickness to provide mechanical support and reduce CTE mismatch effects. This localized differentiation allows the package to achieve low profile while maintaining reliability at the solder joint interface.
Solution Approach 2:
The patent segments the WLCSP package into distinct thickness regions - a central thinner region over the die attach area and a thicker peripheral region. This segmentation allows different parts of the package to serve different functions: the thinner central region reduces profile height while the thicker peripheral region provides structural support and mitigates thermal expansion mismatch with the PCB.
2Length of moving object
If the WLCSP is made thinner to reduce size, then the package becomes more compact, but susceptibility to damage from external stresses increases
Solution Approach 1:
The patent applies local quality by creating different thickness zones within the WLCSP package. The die attach area is made thinner to reduce overall profile height, while the periphery is maintained at greater thickness to provide mechanical support and reduce CTE mismatch effects. This localized differentiation allows the package to achieve low profile while maintaining reliability at the solder joint interface.
Solution Approach 2:
The patent segments the WLCSP package into distinct thickness regions - a central thinner region over the die attach area and a thicker peripheral region. This segmentation allows different parts of the package to serve different functions: the thinner central region reduces profile height while the thicker peripheral region provides structural support and mitigates thermal expansion mismatch with the PCB.
Data Source
AI summary
A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.