Variable-Tier Pitch Memory Stack for Structural Integrity
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in maintaining structural integrity during fabrication due to the large aspect ratio and height of conductive and dielectric structures, leading to potential collapse and reduced memory density.
Innovation Solution
A microelectronic device design featuring a stack structure with alternating tiers of insulative and conductive materials, where different regions have varying tier pitches and thicknesses, facilitating improved fabrication and memory cell performance by reducing the aspect ratio and enhancing the replacement gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of tiers of conductive structures is increased to provide additional memory density, then memory density is improved, but the height of the stack and aspect ratio of openings increase leading to structural collapse
Solution Approach 1:
The stack structure is divided into multiple regions with different tier pitches. Lower regions have larger tier pitches while upper regions have smaller tier pitches, allowing the structure to be segmented into zones with different mechanical properties suitable for their respective positions in the stack.
Solution Approach 2:
Different regions of the stack are assigned different tier pitch characteristics based on their local requirements. The lower regions with larger tier pitches provide structural support where openings are widest, while upper regions with smaller tier pitches maximize memory density where the stack is more constrained.
2Ease of manufacture
If uniform tier pitch is used throughout the stack, then manufacturing is simplified, but structural collapse occurs in lower regions with large openings
Solution Approach 1:
The uniform structure is segmented into multiple regions with different tier pitches. This segmentation allows each region to be optimized independently - lower regions use larger pitches for structural integrity while upper regions use smaller pitches for density, resolving the conflict between simplicity and reliability.
Solution Approach 2:
The tier pitch parameter is changed across different regions of the stack rather than maintaining a uniform value. This parameter variation allows the structure to adapt to different mechanical constraints at different heights, preventing collapse in lower regions while maintaining manufacturability.
3Reliability
If larger tier pitch is used in lower regions, then structural integrity is improved, but memory density in those regions is reduced
Solution Approach 1:
Each region of the stack is assigned a tier pitch appropriate to its local requirements. Lower regions have larger pitches for structural support, while upper regions have smaller pitches for maximum density. This local optimization ensures that no single region compromises the overall performance for the benefit of another.
Solution Approach 2:
The solution moves from a one-dimensional uniform pitch approach to a multi-dimensional variable pitch approach, where the pitch varies along the vertical dimension of the stack. This allows simultaneous optimization of structural integrity in lower regions and memory density in upper regions by exploiting the vertical dimension for gradient pitch variation.
Data Source
AI summary
A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.