Variable Size TLB Cache Lines for High-Throughput Translation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory translation systems face inefficiencies in handling virtual to physical address translation, particularly when dealing with small buffers or poorly compressible page table entries (PTEs), as they struggle to balance throughput and generality, leading to suboptimal cache hit rates and increased miss frequencies.
Innovation Solution
A translation lookaside buffer (TLB) system that stores compressed cache lines with variable size coverage, allowing for flexible address translation by dynamically adjusting cache line ranges based on compression levels and page sizes, and reissuing requests when necessary to maintain high throughput and generality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PTEs are compressed and stored in cache lines with assumed address range, then cache hit rate is improved and throughput is increased, but determination of cache hits and misses becomes complicated and additional reissues may be generated
Solution Approach 1:
The system performs preliminary compression of PTEs and stores them in cache lines with an assumed address range before actual access. By pre-compressing and pre-storing with assumed ranges, the system achieves high throughput while managing complexity through a structured fill-pending mechanism that tracks actual ranges separately.
Solution Approach 2:
The patent introduces an intermediary mechanism (fill-pending status and queued requests) that mediates between the compressed cache storage and actual address translation needs. This intermediary layer allows the system to handle the complexity of variable-size coverage without impacting the core translation throughput.
2Reliability
If cache lines store compressed PTEs with variable size coverage, then cache efficiency improves, but the system loses generality for small buffers or poorly compressible PTEs
Solution Approach 1:
The system dynamically adjusts cache line coverage based on compression success and PTE characteristics. For highly compressible PTEs, the system uses larger assumed ranges to improve cache efficiency, while for poorly compressible or small buffer PTEs, the system automatically reduces coverage to maintain generality. This dynamic adaptation resolves the contradiction between efficiency and versatility.
Solution Approach 2:
The patent changes the parameter of cache line coverage size based on PTE compressibility and buffer characteristics. By making the coverage parameter variable rather than fixed, the system can optimize for cache efficiency when possible while maintaining generality for edge cases, thus resolving the contradiction between reliability and adaptability.
3Productivity
If assumed address range is chosen to be large for high-throughput cases, then throughput is maximized, but reissues are generated when actual range is smaller
Solution Approach 1:
The system uses partial compression and partial cache line filling based on actual PTE data. Instead of always using maximum assumed ranges, the system fills cache lines with the actual number of PTEs returned, using excessive action only when it benefits throughput without causing harmful reissues. This partial approach balances throughput maximization with reissue minimization.
Solution Approach 2:
The patent implements feedback through the fill-pending mechanism that tracks the relationship between assumed and actual address ranges. When reissues are generated, the system learns from this feedback and adjusts future cache line allocations, choosing assumed ranges that avoid reissues in the majority of cases while maintaining high throughput.
Data Source
AI summary
One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills.