Variable-Length Trace Cache for Higher Fetch Bandwidth

Solution Overview

Problem

Trace caches in traditional processor designs face challenges due to increased power consumption and area usage, and the cost associated with unexpected branch exits, which have impeded their practical implementation.

Innovation Solution

Implementing a hierarchical trace cache system with a larger L2 trace cache and using signature-based prefetching, lookahead techniques, and a fast array prefetch buffer to enhance performance while reducing power consumption and circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a trace cache is implemented to increase instruction fetch bandwidth, then fetch performance is improved, but power consumption and processor area increase

Engineering Contradiction:

Improveinstruction fetch bandwidthVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The trace cache is divided into multiple sets, each capable of holding traces of different lengths. This segmentation allows the cache to efficiently store and retrieve variable-length traces without requiring a single large cache structure, thereby improving fetch bandwidth while controlling power consumption through selective activation of cache sets.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The trace cache implements dynamic trace length support where each cache set can accommodate traces of varying lengths. The cache control circuitry dynamically adjusts which sets are active and how traces are stored and retrieved, optimizing performance while minimizing power consumption by only activating necessary cache resources.

Inventive Principle:

Principle #15Dynamics

2Productivity

If a trace cache is implemented to increase instruction fetch bandwidth, then fetch performance is improved, but processor area increases

Engineering Contradiction:

Improveinstruction fetch bandwidthVSAvoidprocessor area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The trace cache is divided into multiple sets, each capable of holding traces of different lengths. This segmentation allows the cache to efficiently store and retrieve variable-length traces without requiring a single large cache structure, thereby improving fetch bandwidth while controlling power consumption through selective activation of cache sets.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each cache set is designed to be universal, capable of storing traces of multiple different lengths within the same set. This multi-functionality eliminates the need for separate cache structures for different trace lengths, reducing overall processor area while maintaining high fetch bandwidth through efficient space utilization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If traditional trace cache designs are used, then implementation is simpler, but performance is limited due to fixed trace length constraints

Engineering Contradiction:

Improvetrace length supportVSAvoidcache control complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The trace cache is divided into multiple sets, each capable of holding traces of different lengths. This segmentation allows the cache to efficiently store and retrieve variable-length traces without requiring a single large cache structure, thereby improving fetch bandwidth while controlling power consumption through selective activation of cache sets.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The cache control circuitry dynamically adjusts trace length parameters based on the specific trace being stored or retrieved. By changing the effective trace length parameter for each operation rather than maintaining a fixed length, the system achieves high adaptability while managing complexity through parameter-based control rather than structural complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12547409B2Trace cache that supports multiple different trace lengths

Publication Date: 2026.02.10 APPLE INC

AI summary

Disclosed techniques relate to storing wide traces in a trace cache. In some embodiments, prediction circuitry predicts directions of control transfer instructions. Instruction cache circuitry may cache instructions sequentially in cache lines that store up to a first number of instructions. Trace cache circuitry may identify traces of instruction, store identified traces having up to the first number of instructions in first trace storage circuitry, and store identified traces having up to a second, greater number of instructions in second trace storage circuitry. This may advantageously allow longer traces to be executed from the second trace storage circuitry (without extensive changes to the instruction cache and processor front end, in some embodiments, due to the limited trace length for the first trace storage circuitry).