Variable Track Routing for IC Non-Default Design Rules
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Solution Overview
Problem
NDR routing in integrated circuits (ICs) complicates design rule checking and introduces a gap between pre-routing and post-routing timing estimates due to increased difficulty in maintaining design rules and estimating timing benefits.
Innovation Solution
A variable track based NDR routing system that utilizes pre-defined tracks with varying pitches, widths, and spacings to assign and optimize NDR constraints, allowing for successful routing of nets with NDRs while simplifying design rule checking and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NDR routing is used to change resistance and capacitance of interconnect conductors, then timing performance is improved, but design rule checking becomes more complicated and the gap between pre-routing and post-routing timing estimates increases
Solution Approach 1:
The patent segments the routing process into distinct phases: pre-routing timing estimation using standard rules, actual routing with NDR constraints, and post-routing timing analysis. By dividing the complex NDR routing process into manageable segments, the system can maintain accurate timing estimates while handling design rule checking in a structured manner.
Solution Approach 2:
The patent performs preliminary timing estimation and constraint assignment before actual routing. NDR constraints are assigned to nets based on timing criticality analysis conducted in advance, allowing the router to prioritize timing-critical nets and apply appropriate NDR rules without complicating the overall design rule checking process.
2Reliability
If NDR constraints are assigned to nets for routing optimization, then timing critical net performance is improved, but the difficulty in maintaining design rules increases
Solution Approach 1:
The patent applies NDR constraints selectively to only those nets that are timing-critical, rather than applying uniform constraints across all nets. This localized approach optimizes timing performance where needed while maintaining standard routing rules for non-critical nets, thereby simplifying overall design rule maintenance.
Solution Approach 2:
The patent changes routing parameters (such as track selection, via placement, and conductor dimensions) locally for nets with NDR constraints while maintaining standard parameters for other nets. This selective parameter modification allows timing optimization without globally complicating design rule maintenance.
3Productivity
If pre-routing timing estimation is performed for NDR routed nets, then routing optimization is enabled, but the gap between pre-routing and post-routing timing estimates increases
Solution Approach 1:
The patent implements a feedback mechanism where post-routing timing analysis results are used to refine pre-routing timing estimates for subsequent routing iterations. This feedback loop gradually reduces the gap between pre-routing and post-routing timing estimates by learning from actual routing outcomes and adjusting estimation models accordingly.
Solution Approach 2:
The patent replaces detailed physical routing simulation with analytical timing estimation models for pre-routing analysis. By using simplified mathematical models that capture the essential behavior of NDR routing without requiring full physical simulation, the system achieves reasonable timing estimates efficiently while minimizing the gap through iterative refinement.
Data Source
AI summary
A device including first track groups on a first conductive layer of an integrated circuit. Each of the first track groups including at least one of a different first track group pitch, a different first track group spacing, and a different first track group width than the other first track groups. Where each of the first track groups includes first tracks that have at least one of a different first track width and a different first track spacing than the first tracks in the other first track groups.