Variable-Length TSV Assembly for Heterogeneous Chip Routing
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Solution Overview
Problem
Conventional semiconductor packaging processes face challenges in efficiently routing electrical connections for heterogeneous semiconductor devices with increasing complexity and shrinking scale, particularly in forming through-silicon vias (TSVs) to reach different devices within the assembly.
Innovation Solution
The implementation of semiconductor device assemblies with TSVs of varying lengths, formed after preliminary assembly and optional testing, allowing for efficient electrical connectivity between devices by using front-side and additional device pads, and enabling testing without damaging the bond pads, followed by encapsulation and rear-surface thinning for TSV formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging processes are used to route electrical connections for heterogeneous semiconductor devices, then the assembly can be manufactured with standard processes, but the complexity of routing connections increases and the scale shrinks making efficient connectivity difficult to achieve
Solution Approach 1:
The patent segments the electrical connection routing into two distinct phases: (1) preliminary assembly and testing of devices on the substrate, and (2) subsequent formation of TSVs through the substrate after assembly. This segmentation allows each phase to be optimized independently, reducing overall complexity while maintaining high connectivity efficiency.
Solution Approach 2:
The patent performs preliminary assembly and testing of semiconductor devices on the substrate before forming the TSVs. This preliminary action allows devices to be positioned and validated early in the process, simplifying subsequent TSV routing since the exact device locations and connection requirements are already determined.
2Reliability
If testing is performed on assembled devices, then device functionality can be verified, but mechanical damage may occur to bond pads during the testing process
Solution Approach 1:
The patent applies a protective layer over the bond pads before testing occurs. This beforehand cushioning protects the bond pads from mechanical damage during the testing process while still allowing electrical testing to proceed, thus maintaining reliability verification without the harmful mechanical effects.
3Ease of manufacture
If TSVs are formed before assembly, then the substrate can be prepared in advance, but it becomes difficult to reach different devices within the assembly with appropriate connection lengths
Solution Approach 1:
The patent inverts the conventional sequence by performing assembly and testing first, then forming TSVs through the substrate afterward. This inversion allows the TSV formation process to be tailored to the specific device layout and connection requirements, enabling different TSV lengths to reach different devices optimally while still allowing advance substrate preparation.
Data Source
AI summary
A semiconductor device assembly includes a first semiconductor device having front and rear surfaces, a plurality of front-side pads disposed over the front surface at a first distance from the rear surface, and a plurality of additional device pads disposed over the front surface at a second distance from the rear surface greater than the first distance; a second semiconductor device in contact with a top side of each of the additional device pads; an encapsulant material at least partially surrounding the second semiconductor device and covering a top side of the front-side pads; a first plurality of TSVs, each extending from the rear surface through the first semiconductor device to a bottom side of one of the front-side pads; and a second plurality of TSVs, each extending from the rear surface through the first semiconductor device to a bottom side of corresponding one of the additional device pads.