Variable Tunnel Insulation for Uniform Memory Programming

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Solution Overview

Problem

Semiconductor memory devices face challenges in achieving uniform threshold voltage distribution, which affects programming speed and electrical characteristics due to varying word line resistances caused by different distances of memory cell strings from the X-decoder.

Innovation Solution

The semiconductor memory device adjusts the thickness of tunnel insulating layers and the width of channel plugs based on the position of memory cell strings relative to the X-decoder, ensuring uniform programming speed across memory cells with different word line resistances by applying varying program and pass voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cell strings are arranged at different distances from the X-decoder, then the memory device can accommodate more memory cells, but the word line resistance varies causing non-uniform threshold voltage distribution

Engineering Contradiction:
Improvenumber of memory cellsVSAvoidthreshold voltage distribution uniformity
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the tunnel insulating layer thickness position-dependent. Memory cell strings closer to the X-decoder have thicker tunnel insulating layers, while those farther away have thinner layers. This compensates for the lower word line resistance near the decoder, achieving uniform threshold voltage distribution across all positions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of tunnel insulating layer thickness based on position. By varying this physical parameter across different locations in the memory array, the invention compensates for resistance variations and maintains uniform programming characteristics throughout the device.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If tunnel insulating layer thickness is increased to improve threshold voltage control, then programming precision improves, but programming speed decreases

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidprogramming speed
Core Design Contradiction:
Manufacturing precisionVSSpeed

Solution Approach 1:

Instead of using a uniform tunnel insulating layer thickness, the patent implements position-dependent thickness variation. This allows each region to be optimized locally - thicker layers where needed for control, thinner layers where speed is prioritized - thereby resolving the speed-precision tradeoff.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This adjustment leads to improved threshold voltage distribution and enhanced electrical characteristics by compensating for changes in programming speed and resistance, resulting in more efficient programming operations.

Implementation Method 1

tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder

Methodology Applied
Scientific EffectQuantum tunneling:

Data Source

PatentUS9646698B2Semiconductor memory device tunnel insulating layers included in the plurality of memory cells having different thicknesses according to distances of the plurality of memory cells from the X-decoder
Publication Date: 2017.05.09 SK HYNIX INC
  • US9646698B2 patent drawing
  • US9646698B2 patent drawing
  • US9646698B2 patent drawing

AI summary

A semiconductor memory device includes a plurality of memory cells and an X-decoder. The plurality of memory cells are connected to a word line. The X-decoder is connected to the word line, and applies an operating voltage to the word line. In the semiconductor memory device, tunnel insulating layers included in the plurality of memory cells have different thicknesses according to distances of the plurality of memory cells from the X-decoder.