Variable Validity Bit Placement in Memory Tag Bits
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Solution Overview
Problem
The process of determining whether data is stored in cache memory is processor resource and time intensive due to the comparison of tag bits of memory transactions with tag bits of each valid memory block, leading to increased response times and reduced performance in processing systems.
Innovation Solution
The placement of validity bits within the tag bits of memory blocks is varied based on hash bits of the address, using the hash value to determine the position of the validity bit, reducing the number of comparisons needed and enhancing security by dynamically locating the validity bit within the tag bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If validity bits are placed at fixed positions in tag bits, then memory block validation is straightforward, but processing time and resource consumption increase due to comprehensive tag bit comparisons
Solution Approach 1:
The patent extracts the validity bit from the conventional fixed-position tag structure and relocates it to variable positions within the tag bits. This extraction allows the system to separate validity checking from full tag comparison, reducing the number of comparison operations needed and thereby decreasing memory access time while maintaining processing throughput
2Reliability
If validity bits are placed at fixed positions in tag bits, then implementation is simple, but security against unauthorized access is reduced
Solution Approach 1:
The patent applies asymmetry by placing validity bits at different positions in different memory blocks rather than using a symmetric fixed-position approach. This asymmetric distribution makes it more difficult for unauthorized access attempts to predict or manipulate validity bit locations, thereby improving memory security while the underlying structure remains manageable
3Measurement precision
If comprehensive tag bit comparison is performed for each memory block, then data accuracy is ensured, but processor resource consumption increases
Solution Approach 1:
The patent implements partial action by performing only necessary validity bit comparisons rather than comprehensive tag bit comparisons for each memory block. By checking only the validity bit at the variable position determined by hash bits, the system ensures sufficient data validation accuracy while significantly reducing processor energy consumption
Data Source
AI summary
A system and method access memory blocks in a memory by receiving a memory transaction request from a processing device. First hash bits of the memory transaction request are compared with second hash bits of a first memory block of a memory. Data associated with the first memory block is output to the processing device based on the comparison of the first hash bits with the second hash bits.