Variable-Width Command Address Bus for Memory Packaging
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Solution Overview
Problem
Current memory device packaging configurations, such as PoP, are limited by the number of available pins, restricting the use of memory devices in various applications due to the requirement for specific pin counts for command/address buses, data buses, and control pins, leading to limited packaging options and computing applications.
Innovation Solution
Implementing a variable-width command/address (CA) bus system that dynamically adjusts the number of pins based on the packaging configuration, allowing the same memory die to be used in different packaging scenarios by altering the bus width and clock edge usage, enabling operation in both BGA and PoP configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a PoP configuration is used to achieve compact computing applications, then the vertical stacking of integrated circuit packages is enabled, but the number of available pins is reduced due to periphery-only pin placement
Solution Approach 1:
The command/address bus width is made dynamic and configurable, allowing the memory device to adapt between different bus widths (e.g., 8-bit or 10-bit) based on the packaging configuration. This enables the same memory die to function in both PoP and BGA packages by adjusting the operational parameters rather than the physical structure.
Solution Approach 2:
The patent changes the operational parameter of the command/address bus width to resolve the pin availability constraint. By configuring the bus to use fewer bits when pins are limited (PoP) and more bits when pins are abundant (BGA), the system adapts to different packaging scenarios without requiring physical redesign.
2Ease of manufacture
If the command/address bus uses a fixed width to simplify the interface design, then the interface design is easier, but the memory device cannot be used in different packaging configurations with different pin counts
Solution Approach 1:
The memory device is designed with multi-functionality to operate in multiple packaging configurations (PoP and BGA) using the same die. The command/address bus can dynamically adjust its width to match the available pin count, making the device universal across different form factors and applications.
Solution Approach 2:
The command/address bus width is made configurable rather than fixed, allowing the system to transition between different operational modes. This dynamic adjustment enables the same hardware interface to serve multiple packaging configurations without requiring separate dedicated designs for each package type.
3Speed
If more pins are allocated to the command/address bus to increase the bus width and improve performance, then the data transfer speed is improved, but fewer pins are available for other functions or packaging flexibility
Solution Approach 1:
The command/address bus width is configured dynamically based on the specific packaging scenario. When high performance is needed and pin availability permits (BGA), the bus operates at maximum width for optimal speed. When pins are constrained (PoP), the bus width is reduced accordingly, maintaining functionality while preserving packaging flexibility.
Solution Approach 2:
The system changes the operational parameter of bus width to balance performance and flexibility. By adjusting the number of bits in the command/address bus based on available pin count, the system optimizes data transfer speed within the constraints of each packaging configuration rather than being locked into a fixed high or low performance mode.
Data Source
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AI summary
Embodiments of the invention relate to a variable-width command/address bus (CA bus). In one embodiment, a memory controller includes first logic to determine whether a memory device is in a first mode or a second mode. The memory controller includes second logic to transmit a command to the memory device with a command/address bus having a first width over a first number of clock edges when the memory device is in the first mode, and with the command/address bus having a second width over a second number of clock edges when the memory device is in the second mode.