Variable-width dummy spacers for sub-lithographic SRAM patterning
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Solution Overview
Problem
Current methods for scaling SRAM devices to smaller sizes are limited by photolithographic resolution, and existing spacer patterning technologies cannot adjust the width of patterned features, making it difficult to achieve the required width difference between pull-down and pass-gate NFETs in FinFET devices for stable SRAM operation.
Innovation Solution
A method involving the formation of dummy features with variable widths using conventional lithography, followed by the creation of narrow and super-wide sidewall spacers, which are then used as a hard mask to pattern the substrate, allowing for the formation of sub-lithographic features with adjustable widths and enabling the manufacture of high-density SRAM devices with wider pull-down transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to pattern features, then the manufacturing process is simple and straightforward, but the minimum feature size is limited by photolithographic resolution and cannot be scaled further
Solution Approach 1:
The patterning process is divided into multiple sequential steps: forming sacrificial features, depositing spacer material, etching back to create spacers, removing sacrificial features, and using spacers as masks. This segmentation allows each step to be optimized independently, achieving sub-lithographic dimensions while maintaining process control
Solution Approach 2:
Sacrificial features are formed in advance with specific spacing and widths, and spacer material is deposited beforehand to define the final feature dimensions. These preliminary structures guide the subsequent etching and pattern transfer processes, enabling precise sub-lithographic feature formation
2Manufacturing precision
If spacer patterning is used to create sub-lithographic features, then the minimum feature size can be reduced below photolithographic limits, but the width of patterned features cannot be adjusted
Solution Approach 1:
The sacrificial features are designed with different local widths and spacing to create different spacer widths in different regions. This allows narrow spacers for pass-gate NFETs and wide spacers for pull-down NFETs to be formed in the same process, providing both sub-lithographic precision and width variability
Solution Approach 2:
The widths of sacrificial features and spacing between them are varied as parameters to control the final spacer widths. By changing these input parameters, different output feature widths are achieved, enabling adjustment of transistor channel widths while maintaining sub-lithographic dimensions
3Reliability
If the width of pull-down NFET is increased to be stronger than pass-gate NFET for SRAM stability, then SRAM stability is improved, but the chip area increases
Solution Approach 1:
Instead of increasing transistor width in the planar dimension, the invention uses vertical spacer structures to define the active region width. The spacer height and deposition thickness control the effective channel width, allowing precise area control while achieving the required transistor strength for SRAM stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of high-density SRAM devices with sub-lithographic features, ensuring the pull-down transistors are wider than pass-gate transistors, thereby maintaining SRAM stability during read processes, and allows for the precise control of channel widths in SRAM devices.
Implementation Method 1
etching into the substrate to form separate narrow and wide substrate features in the pattern of the hard mask
Data Source
AI summary
A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.