Variable-Width GAA Nanostructures for Fin Pitch Shrinkage
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) due to increased complexity in the manufacturing process, particularly with the introduction of multi-gate devices like the gate-all-around (GAA) transistor, which requires advanced patterning techniques to achieve efficient gate-channel coupling and reduce short-channel effects.
Innovation Solution
A method for manufacturing semiconductor devices involving the formation of fin structures with varying widths and nano wires or sheets, where a first fin structure with a single stack of nano wires or sheets has a larger width, and a second fin structure with multiple stacks of nano wires or sheets have smaller widths, allowing for design flexibility and concurrent formation to achieve speed gains and aggressive fin pitch shrinkage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor IC dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning or multi-patterning techniques. First, a mandrel structure is formed and patterned, then spacers are deposited and patterned to create additional features. This multi-stage approach enables the formation of complex fin structures with varying widths that would be difficult to achieve with single-step patterning, thereby managing manufacturing complexity while maintaining productivity gains from scaling.
Solution Approach 2:
The patent employs preliminary action by forming mandrel structures and spacer layers before final pattern transfer. The mandrels are prepared in advance with specific geometries, and spacers are pre-deposited with controlled thicknesses. These preliminary structures serve as templates that guide subsequent etching and pattern transfer steps, enabling precise control over fin structure dimensions and reducing the complexity of direct pattern formation.
2Reliability
If multi-gate devices with increased gate-channel coupling are implemented to improve gate control, then device performance improves, but device complexity increases
Solution Approach 1:
The patent implements another dimension by transitioning from planar gate structures to three-dimensional gate-all-around (GAA) configurations. The gate structure wraps around the channel region on multiple sides (two or four sides), providing enhanced gate control through increased gate-channel coupling. This dimensional change allows the gate to control the channel from multiple directions, improving device performance while the systematic fabrication approach manages the associated structural complexity.
Solution Approach 2:
The patent applies nested doll by creating hierarchical structures where gates are nested around channels, and multiple fins are integrated within a shared gate structure. The gate-all-around configuration effectively nests the gate material around the channel region, similar to nested dolls, providing comprehensive control. Multiple fin structures can be nested within a common gate, reducing overall device complexity compared to separate gates for each fin.
3Adaptability or versatility
If spacers with different thicknesses are used to create fins of varying widths, then adaptability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by depositing spacer layers with different thicknesses in different spatial locations. First spacers are formed with a first thickness in certain regions, while second spacers are formed with a second thickness in other regions. This allows different fin structures to have different widths according to local design requirements, enhancing adaptability. The selective thickness control is achieved through localized deposition processes that can precisely control spacer dimensions in specific areas without affecting other regions.
Data Source
AI summary
A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. A left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. The semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. A left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. In addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.