Variable Width Gate Structure for FinFET Process Margin
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to secure a manufacturing process margin and improve yield while using a single diffusion break in multi-gate transistors, which are prone to short channel effects and require precise control over fin-type patterns and gate structures.
Innovation Solution
A semiconductor device design featuring first and second fin-type patterns with specific field insulating films and gate structures, where the first gate structure has a wider portion on the first field insulating film and a narrower portion on the second field insulating film, with spacers to maintain process control and yield improvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single diffusion break is used in multi-gate transistors, then manufacturing complexity is reduced, but manufacturing process margin and yield deteriorate
Solution Approach 1:
The gate structure is segmented into multiple portions (first gate portion, second gate portion, third gate portion) with different widths. Each portion corresponds to a different fin region, allowing independent optimization of diffusion break characteristics for each segment while maintaining overall manufacturing simplicity.
Solution Approach 2:
Different regions of the gate structure are assigned different local properties through varying gate widths. The first gate portion has a wider width for better control in its region, while the second gate portion has a narrower width suited for its region, optimizing performance locally without increasing overall manufacturing complexity.
2Reliability
If multi-gate transistor structure is used, then current control capability is improved, but short channel effects worsen
Solution Approach 1:
The invention transitions from a planar gate structure to a multi-gate three-dimensional structure. Multiple gates wrap around the fin regions, providing control from multiple dimensions (front, back, and sidewalls), which significantly improves current control capability and suppresses short channel effects that plague conventional planar transistors.
Solution Approach 2:
The gate structures are nested around the fin regions in a multi-layer configuration. The first, second, and third gate portions are positioned at different heights and locations, creating a nested arrangement that provides comprehensive control over the channel region while maintaining effective gate length control.
Data Source
AI summary
A semiconductor device comprising a first field insulating film around at least a part of a first fin type pattern and at least a part of a second fin type pattern, a second field insulating film between the first fin type pattern and the second fin type pattern and protruding from the first field insulating film and a first gate structure which extends over the first and second field insulating films in a second direction intersecting with a first direction, and includes a first portion on the first field insulating film, and a second portion on the second field insulating film, wherein a first width of the first portion of the first gate structure is greater than a second width of the second portion of the first gate structure.