Variable-Width Memory Modules for Signal Integrity
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Solution Overview
Problem
The number of memory modules that can be connected to a single channel in memory systems has decreased with increased signaling rates, leading to degraded signaling integrity and limited signal rates.
Innovation Solution
A memory system that includes a memory host connected to a memory module capable of supporting different data widths, allowing for the configuration of multiple memory modules to increase system memory capacity while maintaining signaling integrity and high signaling rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory modules connected to a single channel is increased, then memory resources are extended, but signaling integrity is degraded and signal rates are limited
Solution Approach 1:
The memory module is divided into multiple independent memory devices (e.g., nine DRAM devices) organized into separate banks. Each bank can be independently accessed, allowing the system to maintain high signal rates by activating fewer devices per transaction while still providing extensive total memory capacity through parallel banks.
Solution Approach 2:
The patent introduces a new dimension of organization by creating multiple banks within a single memory module, each bank containing multiple memory devices. This bank-based hierarchical structure allows the system to scale memory capacity vertically (more banks) without proportionally increasing the load on any single signaling channel, thereby maintaining signal integrity.
2Speed
If signaling rates are increased, then data transmission speed is improved, but the number of modules that can be connected to a single channel decreases
Solution Approach 1:
By segmenting the memory module into multiple banks with independent access paths, the system can operate fewer memory devices per transaction at higher signaling rates while achieving equivalent or greater total throughput through parallel bank operations.
Solution Approach 2:
The memory controller dynamically selects which banks to access based on workload requirements, allowing the system to optimize between signaling rate and module count by activating only the necessary number of banks at any given time, thereby maintaining high signal rates even with multiple modules connected.
Data Source
AI summary
A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.