Variable-Width Nanostructures for Dense Gate-All-Around Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits due to increased complexity from scaling down semiconductor IC dimensions, particularly in achieving effective gate control and reducing short-channel effects in multi-gate devices like the gate-all-around transistor (GAA).
Innovation Solution
A method for manufacturing semiconductor devices involves forming nano epitaxy layers and sacrificial layers on a substrate, using photolithography and self-aligned processes to pattern fin structures and gate structures, allowing for concurrent formation of fin structures with varying widths and nano wires or sheets, which enables design flexibility and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and self-aligned processes are used to pattern fin structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the gate structure into multiple segments that wrap around the channel region, creating multi-gate configurations (e.g., double-gate, tri-gate, or gate-all-around structures). This segmentation allows each gate segment to be independently controlled and optimized, improving gate control over the channel while managing the complexity through modular design
Solution Approach 2:
The patent implements nested structures where gate regions are positioned around the channel region in a hierarchical manner. The gate structure is nested within the three-dimensional configuration, with gate segments arranged at different levels and positions surrounding the channel, enabling effective gate control from multiple directions
2Reliability
If gate-all-around structures are used to improve gate control, then gate-channel coupling is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different properties to different regions of the device. The gate structure is specifically configured to wrap around the channel region with optimized dimensions and materials in different areas. The gate-channel interface is engineered with specific characteristics to maximize coupling, while other regions are optimized for their respective functions, allowing effective gate control without uniformly increasing complexity throughout the entire device
Solution Approach 2:
The patent transitions from planar two-dimensional gate structures to three-dimensional gate-all-around configurations. The gate structure extends around the channel region in the vertical and lateral dimensions, providing control from multiple spatial directions. This dimensional change enables superior gate control by enclosing the channel region, maximizing the gate's electric field influence on the channel while utilizing the third dimension to manage the complexity of the overall structure
3Productivity
If fin pitch is aggressively shrunk to increase device density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned processes where the fin structures and gate structures are automatically positioned relative to each other through the patterning sequence. The mandrel structures and spacer formations create self-aligned features that automatically define the fin pitch and gate positioning, reducing the need for additional alignment steps and minimizing the accumulation of positioning errors as device dimensions are scaled down
Solution Approach 2:
The patent performs preliminary patterning actions to define the fin structures and gate structures before final device assembly. The mandrel structures are formed first, followed by spacer deposition and mandrel removal, which pre-establishes the critical dimensions and positions. This preliminary structuring allows for controlled fin pitch shrinkage while maintaining precision through the predetermined geometric relationships established in earlier process steps
Data Source
AI summary
A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.