Variable-Width Data Input for Parallel Pattern Recognition
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Solution Overview
Problem
Pattern-recognition tasks in computing are bottlenecked by the need to search large data streams for multiple patterns, especially in systems with fixed-width devices that are not optimized to handle variable-width data streams, leading to performance slowdowns and bus congestion.
Innovation Solution
A variable-width data input system is implemented, using a pattern-recognition processor with parallel finite state machines and a variable width data control logic that processes data streams of any width by activating only the necessary bytes, allowing for simultaneous evaluation of multiple search criteria without scaling with the number of patterns, thereby maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed-width device processes data one byte at a time, then the device can process data sequentially and maintain simple architecture, but the processing speed decreases and bus capacity is not fully utilized
Solution Approach 1:
The patent implements a variable-width data input mechanism that dynamically adjusts the data width based on the actual data size. The system can receive data in 1-byte, 2-byte, or 4-byte widths and automatically configure the processing path accordingly, allowing the fixed-width device to efficiently handle variable-width data without requiring complex architecture changes.
2Productivity
If multiple patterns are searched sequentially in a data stream, then each pattern can be processed individually with simple logic, but the total processing time increases and creates a computing bottleneck
Solution Approach 1:
The patent combines multiple pattern search operations into a single parallel processing step. The recognition module simultaneously evaluates multiple search criteria against the data stream, allowing multiple patterns to be detected in parallel rather than sequentially, thereby eliminating the bottleneck caused by sequential processing.
Solution Approach 2:
The patent transitions from sequential pattern searching (one-dimensional time-based approach) to parallel pattern searching (multi-dimensional simultaneous evaluation). By introducing parallel processing capability, the system can evaluate multiple search criteria at the same time, adding a temporal dimension to the search process and significantly reducing total processing time.
3Productivity
If a byte-oriented device is used with wider buses, then individual bytes can be accessed, but the full bus capacity is not utilized and performance is reduced
Solution Approach 1:
The patent changes the data width parameter dynamically based on the actual data being processed. Instead of always processing data as single bytes, the system adjusts the data width parameter to match the bus capacity (1-byte, 2-byte, or 4-byte modes), thereby maximizing bus utilization while maintaining compatibility with the byte-oriented processing architecture.
Data Source
AI summary
Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.