Variable Width Superblock Addressing for NAND Flash
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional NAND flash memory devices face challenges with large aggregated block units, leading to increased latency, reduced operational performance, and wasted storage due to inefficient maintenance operations and resource management, particularly in managed NAND devices.
Innovation Solution
The implementation of variable width superblocks, which allow for flexible management of device bandwidth and latency by omitting blocks from some planes, enabling more efficient maintenance operations and reducing operational loss, while maintaining device throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large aggregated block units are used in NAND flash memory, then storage capacity is increased, but maintenance operation time and latency are increased
Solution Approach 1:
The patent segments the large aggregated block unit into multiple smaller sub-blocks that can be independently managed and maintained. This allows maintenance operations to be performed on smaller portions of data simultaneously, reducing the overall maintenance time while preserving the total storage capacity of the aggregated blocks.
2Quantity of substance
If large aggregated block units are used in NAND flash memory, then storage capacity is increased, but operational performance is reduced
Solution Approach 1:
By dividing aggregated blocks into smaller sub-blocks, the system can perform read and write operations on individual sub-blocks independently. This parallelization capability improves operational performance by allowing multiple operations to occur simultaneously across different sub-blocks, while the total storage capacity remains equivalent to the full aggregated block size.
3Device complexity
If traditional fixed-width superblocks are used, then addressing is simplified, but storage efficiency is reduced due to wasted space
Solution Approach 1:
The patent implements variable-width superblocks that can dynamically adjust their size based on the actual data requirements. This allows the superblock structure to adapt to different data patterns and efficiencies, minimizing wasted storage space while maintaining manageable addressing through controller-based width specification.
Solution Approach 2:
The superblock width parameter is made variable rather than fixed, allowing the system to optimize storage efficiency by adjusting the superblock width to match the actual data size. This parameter change enables better space utilization without significantly complicating the addressing mechanism, as the width is controlled by the memory controller.
Data Source
AI summary
Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.