Variant Model Compilation for Analog Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Analog simulators face performance issues due to the lack of optimization in higher-level abstraction models, such as those written in Verilog-A, which reduces simulator efficiency compared to built-in models.
Innovation Solution
A design verification system that selectively compiles analog design blocks into multiple variant models based on parameter sets, generating equivalent networks and optimizing the simulation process by collapsing nodes and branches, thereby improving compilation throughput and reducing extraneous calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If higher-level abstraction models (Verilog-A) are used for analog design blocks, then modeling flexibility is improved, but simulator performance deteriorates due to lack of optimization
Solution Approach 1:
The system performs preliminary analysis of Verilog-A model parameters before simulation to identify constant parameters that can be folded into the matrix structure. This advance preparation enables optimization opportunities to be captured without affecting the flexibility of the original Verilog-A models during simulation execution.
Solution Approach 2:
The system dynamically changes the representation of model parameters by distinguishing between constant and variable parameters. Constant parameters are extracted and incorporated into the simulation matrix during compilation, while variable parameters remain as model inputs during simulation, thereby optimizing performance without sacrificing modeling flexibility.
2Adaptability or versatility
If Verilog-A models are used instead of built-in models, then design flexibility is improved, but compilation throughput deteriorates due to extraneous calculations
Solution Approach 1:
The system extracts constant parameters from Verilog-A model definitions and separates them from variable parameters. This extraction removes extraneous calculation overhead by pre-processing the model parameters, allowing the simulator to skip redundant computations during compilation while preserving the full design flexibility of Verilog-A models.
3Measurement precision
If full Verilog-A model analysis is performed for all design blocks, then model accuracy is maintained, but computational overhead increases
Solution Approach 1:
The system applies partial analysis to Verilog-A models by identifying and processing only the constant parameters that can be folded into the matrix structure, rather than performing complete analysis of all model parameters. This partial action maintains model accuracy for variable parameters while significantly reducing computational overhead by avoiding unnecessary analysis of parameters that don't contribute to optimization opportunities.
Data Source
AI summary
A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and branches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.