Variation-Aware Delay Fault Testing for Carbon Nanotube FETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for detecting process variations and manufacturing defects in integrated circuits, such as carbon nanotube FETs, are inadequate due to their non-linear impact on gate delay, which conventional silicon-based methods cannot effectively address, leading to undetected imperfections during high-volume manufacturing.
Innovation Solution
A variation-aware delay fault testing approach using statistical metrics and random simultaneous parameter variations to grade test pattern sets, integrated with electronic design automation tools for improved testability of process variation-induced faults, involving the generation of random variation scenarios and calculation of total delays through paths to select the highest delay paths for test pattern generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional silicon-based test methods are used, then manufacturing simplicity is maintained, but detection precision of process variation-induced faults deteriorates due to non-linear parameter variations
Solution Approach 1:
The patent transforms the testing approach by changing from fixed deterministic test patterns to randomized test patterns with varying parameters. Random seed values, random permutation indices, and random scaling factors are introduced to create diverse test scenarios that capture non-linear parameter variations, thereby improving detection precision without requiring fundamentally new testing hardware
Solution Approach 2:
The patent creates multiple copies of the circuit under test by generating numerous randomized test patterns that simulate different process variation scenarios. Each randomized test pattern represents a virtual copy of the circuit operating under specific parameter variations, allowing comprehensive fault detection through statistical analysis of multiple copies rather than testing a single physical instance
2Reliability
If random variation scenarios with multiple paths are selected, then fault detection coverage improves, but computational time increases
Solution Approach 1:
The patent performs preliminary actions by pre-generating and storing randomized test patterns and their associated metrics before actual fault detection. The system pre-computes path delays, selects critical paths, and prepares test data structures in advance, so that during actual testing, the system can quickly apply pre-prepared patterns without performing complex computations in real-time, thus reducing computational time while maintaining comprehensive coverage
Solution Approach 2:
The patent applies partial action by selecting only the most critical paths for detailed analysis rather than exhaustively testing all possible paths. The system identifies and focuses computational resources on paths with highest risk or greatest impact, performing excessive action on critical paths while using simplified approaches for less critical paths, thereby achieving high reliability without proportional increases in computational time
Data Source
AI summary
Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.