Varied Epitaxial Source/Drain Structures for SRAM Scaling
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or below, particularly in optimizing multi-gate transistors, due to variability and constraints on process technologies, which affect the performance and integration of SRAM and logic circuits.
Innovation Solution
Implementing varied epitaxial source or drain structures and device types, such as dual epitaxial patterning and separate etching operations for SRAM and logic, allowing independent control of ESD size and composition, and incorporating backside power delivery to reduce interconnect stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure can be maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node or below
Solution Approach 1:
The patent segments the fabrication process into distinct operations: forming first and second epitaxial source/drain structures with different compositions, performing selective recess etching, and implementing separate processing flows for SRAM and logic circuits. This segmentation enables precise control at 10nm node by treating different device regions independently rather than using a monolithic fabrication approach.
Solution Approach 2:
The patent implements local quality by creating epitaxial source/drain structures with different compositions (e.g., SiGe for logic, Si for SRAM) in different spatial regions of the same device. This allows each region to be optimized for its specific function while maintaining overall device integration, resolving the contradiction between precision and complexity.
2Productivity
If multi-gate transistor dimensions are reduced to increase density, then circuit capacity increases, but process constraints become overwhelming
Solution Approach 1:
The patent changes material composition parameters by introducing epitaxial source/drain structures with varying Ge content (e.g., 0-30% Ge for logic, 0-5% Ge for SRAM). This parameter change enables continued scaling of multi-gate transistor dimensions while managing process constraints through material property optimization rather than purely geometric scaling.
Solution Approach 2:
The patent performs preliminary actions by forming epitaxial source/drain structures before final transistor fabrication steps. This preliminary structuring with controlled compositions establishes a foundation that simplifies subsequent processing and enables higher device density without overwhelming process complexity.
3Ease of manufacture
If SRAM and logic circuits share the same epitaxial structure, then fabrication is simplified, but performance optimization is limited
Solution Approach 1:
The patent applies local quality by creating spatially differentiated epitaxial structures where logic circuits receive SiGe-rich material (20-30% Ge) for high mobility, while SRAM circuits receive Si-poor material (0-5% Ge) for stability. This local differentiation maintains reasonable fabrication simplicity while achieving circuit-specific performance optimization.
Solution Approach 2:
The patent segments the epitaxial growth process into separate operations for different circuit regions, allowing independent composition control. This segmentation resolves the contradiction by enabling performance optimization without requiring entirely separate fabrication lines, maintaining ease of manufacture through integrated process flow.
4Power
If epitaxial source/drain structure size is increased for logic performance, then logic circuit performance improves, but SRAM scaling is compromised
Solution Approach 1:
The patent uses local quality to allow larger epitaxial structures in logic regions (improving power performance through higher carrier mobility) while maintaining smaller structures in SRAM regions (enabling scaling). The composition and dimensions are locally optimized for each circuit type within the same integrated device.
Solution Approach 2:
The patent changes the Ge content parameter in epitaxial structures to decouple size constraints from performance requirements. Logic circuits use high-Ge content structures that can be larger, while SRAM uses low-Ge content structures that scale smaller, resolving the contradiction between performance and scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables SRAM scaling without compromising logic performance, reduces power network resistance, and allows for more efficient use of layout space, improving overall circuit density and functionality.
Implementation Method 1
forming a first epitaxial source or drain structure and a second epitaxial source or drain structure
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
Integrated circuit structures having varied epitaxial source or drain structures and device types are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires, each of the second plurality of horizontally stacked nanowires having a lateral width less than a lateral width of each of the first plurality of horizontally stacked nanowires. First epitaxial source or drain structures are at ends of the first plurality of horizontally stacked nanowires, each of the first epitaxial source or drain structures having a maximum lateral width. Second epitaxial source or drain structure are at ends of the second plurality of horizontally stacked nanowires, each of the second epitaxial source or drain structures having a maximum lateral width greater than the maximum lateral width of each of the first epitaxial source or drain structures.