Varied Epitaxial Source/Drain Structures for SRAM and Logic Scaling
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Solution Overview
Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or below, particularly in optimizing multi-gate transistors, due to variability and constraints on semiconductor processes, which affect the performance of SRAM and logic circuits with differing epitaxial source or drain (ESD) requirements.
Innovation Solution
The implementation of varied epitaxial source or drain structures and device types, such as dual epitaxial patterning and separate etching operations for SRAM and logic, allows independent control of ESD size and composition, enabling SRAM scaling without compromising logic performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or below
Solution Approach 1:
The patent divides the fabrication process into separate operations for different device types. Specifically, it implements separate etching operations for SRAM devices and logic devices, allowing each to be optimized independently. This segmentation enables precise control of epitaxial source or drain structure dimensions for each device type without compromising the other, thereby achieving high manufacturing precision at 10 nanometer node while managing process complexity through structured division of operations.
Solution Approach 2:
The patent applies local quality by creating varied epitaxial source or drain structures with different compositions and dimensions tailored to specific device locations. SRAM devices receive epitaxial structures with one set of properties optimized for memory performance, while logic devices receive structures with different properties optimized for logic circuit performance. This localized optimization enables high manufacturing precision for each device type in its specific context.
2Productivity
If multi-gate transistors are scaled down, then device density increases, but process constraints become overwhelming
Solution Approach 1:
The patent segments the multi-gate transistor fabrication into device-type-specific operations. By implementing separate etching processes for SRAM and logic devices, the patent maintains high device density through continued scaling while reducing process constraints through specialized handling of each device type. This segmentation prevents the constraints from becoming overwhelming by addressing each device type's specific requirements independently.
Solution Approach 2:
The patent utilizes parameter changes by varying the epitaxial growth conditions, composition, and dimensions for different device types. For SRAM devices, specific parameters are optimized for memory performance, while for logic devices, different parameters are optimized for logic circuit performance. This ability to change parameters locally allows high device density to be achieved while managing process constraints through flexible parameter optimization.
3Reliability
If varied epitaxial structures are implemented, then electrical performance optimization improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the epitaxial structure formation into separate operations for SRAM and logic devices. By implementing separate etching operations and device-type-specific epitaxial growth, the patent achieves electrical performance optimization for each device type while managing manufacturing complexity through structured segmentation. The complexity is handled systematically through clear separation of operations rather than through unmanageable process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables independent electrical performance optimization for SRAM and logic circuits, improving ESD fill quality and reducing power network resistance, thereby enhancing overall circuit performance and layout flexibility.
Implementation Method 1
varied epitaxial source or drain structures
Data Source
AI summary
Integrated circuit structures having varied epitaxial source or drain structures and device types are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires, each of the second plurality of horizontally stacked nanowires having a lateral width less than a lateral width of each of the first plurality of horizontally stacked nanowires. First epitaxial source or drain structures are at ends of the first plurality of horizontally stacked nanowires, each of the first epitaxial source or drain structures having a maximum lateral width. Second epitaxial source or drain structure are at ends of the second plurality of horizontally stacked nanowires, each of the second epitaxial source or drain structures having a maximum lateral width greater than the maximum lateral width of each of the first epitaxial source or drain structures.