Varied Internal Spacers for Scaled Nanowire Transistor Source-Drain
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Solution Overview
Problem
The scaling of multi-gate transistors to smaller dimensions poses overwhelming constraints on semiconductor processes, limiting the possibility to extend fabrication into the 10 nanometer node or sub-10 nanometer node range.
Innovation Solution
The implementation of integrated circuit structures with varied internal spacers and epitaxial source or drain structures, which involve modulating dimple etch and epitaxial growth to optimize device performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate transistors are scaled to smaller dimensions to increase device density, then the number of functional units per chip increases, but the constraints on semiconductor fabrication processes become overwhelming
Solution Approach 1:
The patent applies local quality by implementing varied internal spacer widths tailored to specific nanowire or nanoribbon channel widths. Different spacer widths are used in different regions of the semiconductor structure to optimize device performance for each channel width, rather than using a uniform spacer width across all devices. This allows the fabrication process to accommodate scaled dimensions while maintaining performance through localized structural variations.
Solution Approach 2:
The patent employs parameter changes by modulating the internal spacer width parameter based on the channel width. By varying this geometric parameter, the invention optimizes the electrical characteristics and performance of scaled transistors, enabling continued scaling while managing fabrication constraints through parameter optimization rather than process complexity increases.
2Ease of manufacture
If conventional fabrication processes are used to maintain manufacturing simplicity, then ease of manufacture is preserved, but the ability to extend fabrication into the 10 nanometer node or sub-10 nanometer node range is limited
Solution Approach 1:
The patent applies preliminary action by forming the internal spacers before the final transistor fabrication steps. The spacers are deposited and patterned in advance, creating a template that guides subsequent processing. This preliminary structuring enables precise feature size control at 10nm and sub-10nm nodes while using relatively simple conventional fabrication processes, as the critical dimensions are established early in the process flow.
3Manufacturing precision
If uniform internal spacers are used to simplify fabrication, then manufacturing precision is maintained, but device performance optimization for specific nanowire or nanoribbon widths is limited
Solution Approach 1:
The patent implements local quality by varying the internal spacer width according to the specific nanowire or nanoribbon channel width. Each region with a particular channel width receives a correspondingly optimized spacer width, creating locally tailored structures that maximize device performance. This approach maintains manufacturing precision through controlled variations rather than uniformity, optimizing reliability for each device type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance and yield by allowing for differential internal spacer widths and epitaxial source or drain structures tailored to specific nanowire or nanoribbon widths, thereby addressing the constraints of scaling multi-gate transistors.
Implementation Method 1
epitaxial growth to optimize device performance and yield
Data Source
AI summary
Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.