Multilayer Chip Varistor ESD Tolerance via Intermediate Conductor Diffusion

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Solution Overview

Problem

Multilayer chip varistors face challenges in achieving improved electrostatic discharge (ESD) tolerance, which is crucial for stable operation in high-speed communication networks like Ethernet standards.

Innovation Solution

The design incorporates a multilayer chip varistor with a specific configuration of electrical conductor groups, where intermediate electrical conductors made of a second conductive material are diffused between internal electrodes, reducing electrical resistance and enhancing ESD tolerance. This configuration includes first and second internal electrodes connected to external electrodes, with intermediate conductors not directly connected to the external electrodes, and the second conductive material is diffused in a low resistance region between the internal electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multilayer chip varistor structure is used, then device complexity is low, but ESD tolerance is insufficient

Engineering Contradiction:
ImproveESD toleranceVSAvoidconductor group configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention divides the electrical conductor system into three distinct groups: first internal electrodes connected to first external electrodes, second internal electrodes connected to second external electrodes, and intermediate electrical conductors positioned between the internal electrodes. This segmentation creates a more complex structure that provides multiple pathways for ESD current dissipation, thereby improving ESD tolerance while maintaining manageable device complexity through systematic organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The intermediate electrical conductors serve as mediators between the first and second internal electrodes. These conductors are not directly connected to external electrodes but facilitate charge distribution and ESD current flow between opposing internal electrodes. This intermediary structure enables improved ESD tolerance by providing additional charge dissipation pathways without requiring direct external connections, thus managing device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If second electrically conductive material is diffused in low electrical resistance region, then ESD tolerance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
ImproveESD toleranceVSAvoiddiffusion control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention applies local quality by concentrating the second electrically conductive material specifically in the low electrical resistance regions between the first and second internal electrodes, rather than uniformly distributing it throughout the entire varistor. This localized diffusion approach improves ESD tolerance by enhancing conductivity where it is most needed for charge dissipation, while minimizing the impact on manufacturing precision by limiting the diffusion zone to specific areas.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention utilizes parameter changes by controlling the diffusion of the second electrically conductive material to alter the electrical resistance characteristics of specific regions. By adjusting diffusion parameters such as temperature, time, and concentration gradients, the manufacturing process achieves the desired low resistance regions that enhance ESD tolerance while maintaining controllable manufacturing precision through established diffusion control techniques.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The configuration significantly improves ESD tolerance, ensuring the varistor can withstand higher discharge voltages and maintain electrical characteristics, making it suitable for high-speed communication networks.

Implementation Method 1

the second electrically conductive material included in the at least one of the first and second intermediate electrical conductors is diffused in the low electrical resistance region

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11594351B2Multilayer chip varistor
Publication Date: 2023.02.28 TDK CORP
  • US11594351B2 patent drawing
  • US11594351B2 patent drawing
  • US11594351B2 patent drawing

AI summary

A multilayer chip varistor includes an element body, first and second external electrodes, and first and second electrical conductor groups. The first electrical conductor group includes a first internal electrode connected to the first external electrode, and a first intermediate electrical conductor opposed to the first internal electrode. The second electrical conductor group includes a second internal electrode including a first electrically conductive material and connected to the second external electrode, and a second intermediate electrical conductor opposed to the second internal electrode. At least one of the first and second intermediate electrical conductors includes the second electrically conductive material. The element body includes a low electrical resistance region between the first and second internal electrodes. The second electrically conductive material is diffused in the low electrical resistance region.