Variable Resistance Layer Formation in 3D ReRAM Using Polysilicon Protection
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Solution Overview
Problem
The challenge in manufacturing highly integrated semiconductor memory devices is the difficulty in forming resistance change films for ReRAM without causing process damage, which affects the dimensional accuracy and position accuracy of circuit patterns.
Innovation Solution
A semiconductor memory device design featuring a variable resistance layer formed in a closed-loop shape around the columnar conducting layers, with a manufacturing method that minimizes process damage by depositing the variable resistance layer on the entire memory area, including inner walls of void portions, and using a polysilicon film as a process protective layer to prevent etching damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistance change film is formed at the sidewall of bit line extending perpendicular to substrate, then highly integrated memory cell array is achieved, but process damage occurs during formation
Solution Approach 1:
A polysilicon protective film is formed on the sidewall of the bit line before forming the resistance change film. This preliminary protective layer prevents process damage during subsequent etching and deposition steps while allowing the resistance change film to be formed at the required location for high integration density.
Solution Approach 2:
The polysilicon film acts as an intermediary protective layer between the bit line sidewall and the etching/deposition processes. This intermediate layer absorbs the process damage that would otherwise directly affect the bit line and resistance change film, enabling reliable formation of highly integrated memory structures.
2Productivity
If line width is reduced for miniaturization, then integration density increases, but dimensional accuracy and position accuracy deteriorate
Solution Approach 1:
The polysilicon protective film is formed in advance to establish a stable reference structure before subsequent processing steps. This preliminary structure maintains dimensional accuracy even as line widths are reduced for higher integration density.
Solution Approach 2:
The protective film changes the physical and chemical parameters of the sidewall surface, providing enhanced stability and precision during subsequent etching and deposition processes. This allows for accurate formation of narrower features while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of variable resistance layers without process damage, improving yield and enabling the creation of highly integrated memory cell arrays with enhanced integration density and operational reliability.
Implementation Method 1
using a polysilicon film as a process protective layer to prevent etching damage
Implementation Method 2
depositing the variable resistance layer on the entire memory area, including inner walls of void portions
Data Source
AI summary
In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.