Varying Diameter Via Layer for Flip Chip Stress Management
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Solution Overview
Problem
Flip chip technology faces issues with delamination of passivation layers due to shear and tensile stresses during assembly and usage, which can lead to device failure and reduced yield, as current solutions that mitigate shear stress exacerbate tensile stress failure modes.
Innovation Solution
The implementation of a varying diameter via layer in the passivation layer, where interior region vias are larger than perimeter region vias, to distribute tensile stress effectively while maintaining small vias in the perimeter region to reduce shear stress, thereby balancing stress distribution and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If small vias are used in the perimeter region to reduce shear stress, then shear stress damage is reduced, but tensile stress concentration increases
Solution Approach 1:
The patent applies different via diameters in different regions of the passivation layer. Perimeter region vias have smaller diameters to reduce shear stress, while interior region vias have larger diameters to reduce tensile stress concentration. This local differentiation allows each region to be optimized for its specific stress conditions.
2Strength
If large vias are used in the interior region to reduce tensile stress, then tensile stress damage is reduced, but shear stress damage increases
Solution Approach 1:
The patent implements a spatially varying via diameter design where interior region vias are larger to handle tensile stress and perimeter region vias are smaller to handle shear stress. This local quality approach ensures each via is sized appropriately for the dominant stress mode in its region.
3Ease of manufacture
If uniform via size is used throughout the passivation layer, then manufacturing is simplified, but stress distribution is unbalanced
Solution Approach 1:
The patent divides the passivation layer into distinct regions (interior and perimeter) with different via sizes optimized for local stress conditions. This requires more complex manufacturing processes but achieves balanced stress distribution and prevents delamination.
Solution Approach 2:
The patent segments the via structure into two distinct groups based on location: interior region vias with larger diameters and perimeter region vias with smaller diameters. This segmentation allows independent optimization of each via group for its specific mechanical environment.
Data Source
AI summary
An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.