Nonvolatile Memory Device With Varying Dielectric Constants
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face interference issues between adjacent memory cells due to downscaling, leading to malfunction, particularly in three-dimensionally stacked configurations where the distance between cells is reduced, causing electrical effects to impact adjacent channels and affecting memory cell thresholds.
Innovation Solution
A nonvolatile semiconductor memory device design featuring control gate electrodes and intercellular dielectric films with varying dielectric constants, where the dielectric constant between a control gate electrode and an adjacent channel is lower than between the electrode and the same channel, reducing electrical interference by controlling the capacitance and preventing threshold variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the electrode film and dielectric film are thinned to increase the number of stacked films for higher degree of integration, then the memory capacity increases, but the distance between memory cells decreases causing interference between adjacent memory cells
Solution Approach 1:
The patent applies local quality by creating different dielectric constant regions within the memory structure. Specifically, a first dielectric layer with a first dielectric constant is formed between the control gate electrode and the active region, while a second dielectric layer with a second dielectric constant is formed between the control gate electrode and the intercellular dielectric film. This spatial differentiation of dielectric properties allows the structure to simultaneously achieve thin film dimensions for high integration and controlled electrical isolation to prevent interference between adjacent cells.
2Productivity
If downscaling is performed to increase degree of integration, then cost per bit decreases, but interference between adjacent memory cells occurs leading to malfunction
Solution Approach 1:
The patent employs parameter changes by varying the dielectric constant parameter across different regions of the memory structure. The first dielectric layer has a different dielectric constant than the second dielectric layer, allowing optimization of electrical characteristics. This parameter differentiation enables the structure to maintain reliable operation at scaled dimensions by controlling the electrical field distribution and reducing coupling effects between adjacent memory cells, thereby preventing malfunction while achieving high integration.
3Quantity of substance
If the distance between memory cells is reduced to increase integration density, then memory capacity increases, but electrical effects impact adjacent channels affecting memory cell thresholds
Solution Approach 1:
The patent uses intermediary dielectric layers to mediate the electrical interaction between the control gate electrode and adjacent structures. The first dielectric layer acts as an intermediary between the control gate electrode and the active region, while the second dielectric layer serves as an intermediary between the control gate electrode and the intercellular dielectric film. These intermediary layers with controlled dielectric constants provide electrical isolation that prevents threshold voltage shifts in adjacent memory cells, enabling high integration density without compromising manufacturing precision of memory cell characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces electrical interference between memory cells, preventing malfunction even at reduced distances, thereby maintaining reliable data storage and retrieval in densely packed memory arrays.
Implementation Method 1
average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode being lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.