Varying Gate Structures for Multi-Threshold Voltage Integration
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Solution Overview
Problem
Existing semiconductor devices require multiple discrete designs for different functions, leading to increased system complexity and cost due to the need for varying device characteristics like threshold voltage and switching speed, which complicates integrated circuit fabrication.
Innovation Solution
An integrated circuit with a varying gate structure having different gate stacks in different regions of the substrate, allowing for field-effect transistors with distinct threshold voltages to be fabricated in a single process, enabling optimization of leakage power consumption and speed by tuning the thickness of gate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple discrete devices with different designs are used to optimize different functions, then device performance is improved, but system complexity and cost increase
Solution Approach 1:
The patent applies local quality by creating different gate stack configurations (varying thicknesses of gate electrode layers, gate dielectric layers, and work function layers) in different regions of the same integrated circuit substrate. This allows each region to have optimized characteristics for its specific function (logic or memory) while maintaining a unified fabrication process, thereby improving device performance without increasing system complexity
2Reliability
If multiple discrete devices with different designs are used to optimize different functions, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements universality by designing a single integrated circuit substrate that can simultaneously host both logic devices and memory devices with different optimized characteristics. The unified fabrication process uses the same base materials and processing steps across the entire substrate, with regional variations achieved through selective masking and etching, thereby reducing manufacturing cost while maintaining optimized performance for different functions
3Reliability
If varying gate structures with different thicknesses are fabricated, then threshold voltage optimization is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the integrated circuit substrate into distinct regions (logic region and memory region) and applying different gate stack thickness configurations to each region. This is achieved through selective masking and etching processes that create region-specific variations in gate electrode and gate dielectric layers, allowing threshold voltage optimization for each device type while maintaining a relatively simple unified fabrication process
Data Source
AI summary
Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).