Varying Storage Cell Gate Node Dimensions in 3D NAND Stacks
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Solution Overview
Problem
The manufacturing of three-dimensional memory devices faces challenges in forming uniform circuit structures as the storage cell stack grows in height, making it difficult to apply consistent processing conditions across the entire stack, particularly affecting the formation of storage gate nodes at the bottom.
Innovation Solution
The design modulates the shape and form of storage cell gate nodes along the depth of the stack, with nodes at the bottom being less wide and thinner, and uses varying poly-silicon layer thickness and depth to facilitate uniform processing, employing techniques like anisotropic plasma etching and modified deposition parameters to ensure complete processing across the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the storage cell stack height is increased to increase storage density, then storage density is improved, but manufacturing precision deteriorates due to difficulty in applying uniform processing conditions across the entire stack
Solution Approach 1:
The patent applies local quality by making the storage cell gate nodes have different dimensions at different positions within the stack. Specifically, gate nodes at lower levels are formed with smaller lateral dimensions (width and thickness) compared to those at upper levels. This local variation compensates for the reduced processing effectiveness at lower stack positions, enabling uniform processing conditions to be achieved throughout the entire high-density stack.
2Quantity of substance
If the storage cell stack height is increased to increase storage density, then storage density is improved, but ease of manufacture deteriorates due to difficulty in forming uniform circuit structures
Solution Approach 1:
The patent makes different parts of the storage cell gate nodes have different dimensions - specifically, gate nodes at lower levels have smaller lateral dimensions while those at upper levels have larger lateral dimensions. This local differentiation simplifies the manufacturing process by accommodating the reduced processing effectiveness at lower stack positions, thereby improving ease of manufacture while maintaining high storage density.
3Manufacturing precision
If uniform processing conditions are applied across the entire stack, then manufacturing precision is improved, but storage density deteriorates due to inability to form proper gate nodes at the bottom of the stack
Solution Approach 1:
The patent applies parameter changes by systematically varying the lateral dimensions of storage cell gate nodes as a function of their position within the stack. Gate nodes at lower levels are formed with smaller width and thickness parameters, while gate nodes at upper levels have larger parameters. This parameter variation enables uniform processing conditions to be applied across the entire stack while still achieving proper gate node formation at all levels, thereby maintaining both manufacturing precision and storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of uniform and functional storage cell stacks with increased density, improving the manufacturing process and storage capacity of three-dimensional NAND FLASH memory devices.
Implementation Method 1
uses varying poly-silicon layer thickness and depth to facilitate uniform processing, employing techniques like anisotropic plasma etching
Data Source
AI summary
An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.