Varying Tier Pitch in Vertical Memory Stacks to Prevent Collapse
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in maintaining structural integrity during fabrication due to the large aspect ratio and height of conductive and dielectric structures, leading to potential collapse and reduced memory density.
Innovation Solution
A microelectronic device design featuring a stack structure with alternating tiers of insulative and conductive materials, where different regions have varying tier pitches and thicknesses, facilitating improved fabrication and memory cell performance by reducing the aspect ratio and enhancing the replacement gate process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of tiers of conductive structures is increased to provide additional memory density, then memory density is improved, but the height of the stack and aspect ratio of openings increase leading to structural collapse
Solution Approach 1:
The stack structure is divided into multiple regions with different tier pitches. Lower regions have larger tier pitches while upper regions have smaller tier pitches, allowing the structure to be segmented into zones with different mechanical properties optimized for their specific functions.
Solution Approach 2:
Different regions of the stack are assigned different tier pitches based on local requirements. The lower regions with larger pitches provide structural support where openings are most vulnerable to collapse, while upper regions with smaller pitches maximize memory density where structural support is less critical.
2Ease of manufacture
If uniform tier pitch is used throughout the stack, then fabrication is simplified, but structural collapse occurs in regions with large aspect ratio openings
Solution Approach 1:
The uniform structure is segmented into multiple regions with different tier pitches. This segmentation allows each region to be optimized independently - lower regions use larger pitches for structural integrity while upper regions use smaller pitches for density, resolving the conflict between fabrication simplicity and structural reliability.
Solution Approach 2:
The tier pitch parameter is changed across different regions of the stack rather than maintaining a uniform value. This parameter change allows optimization of structural integrity in lower regions while maximizing density in upper regions, preventing collapse without significantly complicating fabrication.
3Reliability
If larger tier pitch is used to prevent dielectric material collapse, then structural integrity is improved, but memory cell spacing increases reducing memory density
Solution Approach 1:
The stack is segmented into lower regions with larger tier pitches for structural integrity and upper regions with smaller tier pitches for high density. This segmentation allows each region to be optimized for its primary function without compromising the other.
Solution Approach 2:
Different tier pitch values are assigned to different local regions based on their specific requirements. Lower regions near the substrate use larger pitches where structural support is critical, while upper regions use smaller pitches where memory density is the priority.
Data Source
AI summary
A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.