VBPR Via Spacer Layout to Prevent Gate Tip Shorting
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Solution Overview
Problem
Increasing density and decreasing spacing in semiconductor chips lead to unwanted interactions such as shorting and parasitic capacitance between the signal layer and power layer, which existing techniques like buried power rails and air gaps do not adequately address.
Innovation Solution
A semiconductor device with a via to backside power rail (VBPR) is formed, where a via spacer separates the VBPR from adjacent gates, preventing shorting and maintaining parasitic capacitance below a threshold, and a method involving a substrate with FETs, dummy gate structures, and a via spacer around the VBPR is used to create a backside power rail, allowing connection to source/drain regions without spacer interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the density of devices on semiconductor chips is increased and spacing is decreased, then device integration is improved, but unwanted interactions such as shorting and parasitic capacitance between signal layer and power layer occur
Solution Approach 1:
The power delivery network is moved from the front side to the back side of the semiconductor chip, utilizing the third dimension (vertical stacking) to separate power and signal layers. This dimensional reorganization allows high device density on the front side while placing the power rail on the back side, eliminating parasitic capacitance and shorting issues between signal and power layers.
Solution Approach 2:
The chip is divided into two separate functional surfaces: the front side for signal processing and the back side for power delivery. This segmentation separates the signal layer and power layer into distinct physical locations, preventing unwanted interactions while maintaining high integration density on the front side.
2Area of stationary object
If a via to backside power rail is formed close to gates to save space, then area utilization is improved, but shorting between the via and gate tip occurs
Solution Approach 1:
A via spacer is introduced as an intermediary dielectric structure between the via to backside power rail and the gate tip. This via spacer acts as a physical barrier that prevents direct contact and potential shorting, while allowing the via to be positioned close to the gate for optimal area utilization.
Solution Approach 2:
The via spacer is formed in advance during the fabrication process to preemptively prevent shorting between the via and gate tip. By establishing this protective dielectric barrier before final via formation, the design ensures reliability while maintaining compact layout.
3Object-affected harmful factors
If buried power rails and air gaps are used to address unwanted interactions, then parasitic capacitance is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of adding complex structures like buried power rails or air gaps within the front side, the solution inverts the conventional approach by placing the power rail on the back side of the chip. This inversion simplifies the manufacturing process while effectively eliminating parasitic capacitance, avoiding the need for complex additional structures.
Data Source
AI summary
One or more systems, devices and/or methods of fabrication provided herein relate to forming a via to backside power rail (VBPR) on a semiconductor device. According to one embodiment, a VBPR with a via spacer is formed before a late gate cut is performed to create a replacement metal gate (RMG), wherein the via spacer prevents a short circuit between the VBPR and the RMG. Further, the via spacer is removed in locations on the VBPR where a source/drain region is adjacent to the VBPR, allowing a conductive connection between the VBPR and the adjacent source/drain region.