VC-EBI Test Patterns for Same-Type Doping Short Detection

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Solution Overview

Problem

Current wafer-level testing techniques, such as VC-EBI, struggle to detect shorting between neighboring source or drain regions of the same doping type, which is a common defect in IC designs, as they do not result in electric charge transfer and hence are not detectable by existing methods.

Innovation Solution

The introduction of specially designed VC-EBI test patterns that can detect shorting between adjacent source or drain structures by utilizing combinations of test patterns with different doping types, allowing for the detection of electrical defects through changes in secondary electron yield in positive and negative mode VC-EBI imaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional VC-EBI testing is used, then the testing process is simple and fast, but it cannot detect shorting between same-type doping regions

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidtest pattern complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The test pattern is segmented into multiple regions with different doping types (first doping type and second doping type) arranged in an interdigitated configuration. This segmentation allows the system to detect shorting defects between same-type doping regions by comparing signals from adjacent regions with different doping characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the test pattern are assigned different local doping qualities (first doping type vs. second doping type) to create detectable signal differences. The interdigitated arrangement ensures that each region maintains its unique doping characteristic, enabling localized defect detection through signal comparison.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If same-type doping regions are tested together, then manufacturing efficiency is maintained, but defect detection accuracy decreases

Engineering Contradiction:
Improveshorting detection accuracyVSAvoidwafer testing throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The test pattern introduces intermediary reference regions with alternating doping types that serve as mediators for detecting shorting defects. These intermediary regions provide a baseline signal that can be compared against test regions, enabling accurate defect detection without requiring separate testing passes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The test pattern merges multiple testing functions into a single integrated structure by combining first doping type regions and second doping type regions in an interdigitated arrangement. This merging allows simultaneous detection of various defect types in one testing operation, maintaining productivity while improving precision.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the detection of shorting between same-type doping regions, providing early defect detection and improving the accuracy of wafer-level testing, thereby enhancing the quality control of semiconductor IC devices.

Implementation Method 1

allowing for the detection of electrical defects through changes in secondary electron yield in positive and negative mode VC-EBI imaging

Methodology Applied
Scientific EffectSecondary electron yield:

Data Source

PatentUS20240361381A1In-line electrical detection of defects at wafer level
Publication Date: 2024.10.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240361381A1 patent drawing
  • US20240361381A1 patent drawing
  • US20240361381A1 patent drawing

AI summary

In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.