VC Image Simulation for Ribbon FET Defect Localization
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in multi-gate transistors as device dimensions scale below the 10 nanometer node, particularly in bulk silicon substrates, is compounded by the trade-off between feature patterned dimension and spacing constraints in lithographic processes, necessitating improved defect detection methods in integrated circuit fabrication.
Innovation Solution
Implementing voltage contrast (VC) image simulation capability using electron beam inspection and predictive analysis to determine defect presence without a reference VC image, by generating a 'golden' reference image through layout search and connectivity techniques, and utilizing a physics-based algorithm to predict VC brightness levels based on metal connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar 2D transistors to three-dimensional multi-gate structures (tri-gate, gate-all-around nanowires). This dimensional change allows the gate to control the channel from multiple directions (top and sidewalls), providing superior electrostatic control and short channel effect suppression at scaled dimensions while maintaining high device density through vertical stacking.
Solution Approach 2:
The patent employs composite material structures including silicon-germanium (SiGe) sacrificial layers combined with silicon nanowire channels, and high-k dielectric materials combined with metal gate electrodes. These composite materials enable precise control over channel properties, mobility enhancement, and effective gate control at nanoscale dimensions.
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing complexity decreases, but mobility improvement and short channel control are compromised
Solution Approach 1:
The patent applies selective local quality modifications by forming silicon-germanium sacrificial regions only in specific areas where nanowire release is needed, while maintaining bulk silicon substrate elsewhere. This localized approach enables complex 3D multi-gate structures to be fabricated on cost-effective bulk silicon without requiring entire wafers to be processed as sophisticated silicon-on-insulator substrates.
3Manufacturing precision
If lithographic processes are used to pattern features at smallest dimensions, then critical dimension is reduced, but spacing between features becomes constrained
Solution Approach 1:
The patent utilizes self-aligned spacer formation processes where sacrificial nanowires are released and positioned in three-dimensional space, then surrounded by conformal spacer materials. This 3D self-alignment approach eliminates the need for additional lithographic patterning steps that would further constrain feature spacing, allowing critical dimensions to be defined by deposition thickness rather than lithographic resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient defect detection in integrated circuits by reducing the need for reference images, saving time and improving the accuracy of defect localization through simulated VC images, thereby enhancing the fabrication process of nanowire and FinFET devices.
Implementation Method 1
voltage contrast (VC) image simulation capability using electron beam inspection
Implementation Method 2
when exposed to an e-beam
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, an integrated circuit structure has layouts of differing brightness when exposed to an e-beam.