VCAT Deskewing Logic Using SDRAM Frame Status Tables
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Solution Overview
Problem
SONET/SDH systems face challenges in efficiently mapping high-speed Ethernet signals due to mismatched bandwidths, leading to bandwidth wastage, and require effective deskewing methods to manage varying path delays and inactive members within Virtual Concatenation Groups (VCGs) during Link Capacity Adjustment Scheme (LCAS) operations.
Innovation Solution
A deskewing method utilizing write and read logic coupled with SDRAM and a frame status table to manage and reorder VCG members, accounting for justifications, path delays, and inactive members, ensuring minimal latency and efficient bandwidth utilization by maintaining a state table and using a temporary buffer for data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional SONET/SDH mapping schemes are used for high-speed Ethernet signals, then bandwidth allocation is simplified, but significant bandwidth wastage occurs due to mismatched bandwidths
Solution Approach 1:
The patent divides a high-speed Ethernet signal into multiple lower-rate SONET/SDH members forming a Virtual Concatenation Group (VCG). By segmenting the Ethernet signal across multiple members (e.g., splitting 10Gbps Ethernet into multiple STS-1 or VT-6 members), the system achieves efficient bandwidth utilization without significant wastage, while maintaining manageable mapping complexity through standardized segmentation procedures.
2Adaptability or versatility
If VCG members traverse different network paths to accommodate flexibility, then path routing adaptability improves, but path delay variations cause skewing that requires complex deskewing management
Solution Approach 1:
The patent applies preliminary deskewing by buffering incoming VCG members in SDRAM before reassembly. The buffer compensates for path delay variations proactively, ensuring that members are synchronized before being reconstructed into the original signal. This preliminary buffering action simplifies the overall deskewing management by handling delay variations in a centralized manner rather than requiring complex real-time adjustment mechanisms throughout the network.
Solution Approach 2:
The patent introduces an intermediary deskewing buffer (SDRAM) between the VCG member inputs and the reassembly process. This intermediary component absorbs path delay variations and provides a standardized interface for signal reconstruction, simplifying the management of skewing caused by flexible path routing while maintaining adaptability.
3Loss of energy
If LCAS operations dynamically adjust VCG member count to match bandwidth needs, then bandwidth efficiency improves, but handling inactive members and maintaining synchronization becomes more complex
Solution Approach 1:
The patent implements self-service deskewing where the system automatically manages inactive VCG members during LCAS operations. The deskewing buffer and control logic autonomously handle the addition and removal of members, maintaining synchronization without requiring manual intervention. This self-managing approach improves bandwidth efficiency through dynamic LCAS operations while containing complexity within the automated control mechanism.
4Reliability
If buffer size is increased to handle maximum path delay variations, then deskewing reliability improves, but memory usage and latency increase
Solution Approach 1:
The patent employs dynamic buffer management where the SDRAM buffer size and allocation are adapted based on actual path delay variations rather than being fixed at maximum capacity. The system dynamically adjusts buffer resources to match current network conditions, maintaining deskewing reliability while minimizing average latency by avoiding consistently large buffer allocations when not needed.
Data Source
AI summary
Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.