Vertical Capacitive Depletion FET With Segmented Drift Regions
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Solution Overview
Problem
Power transistors face a trade-off between high breakdown voltage (BV) and low on-resistance (RON), with increasing dopant concentration and drift region thickness improving both characteristics but also increasing fabrication complexity and cost.
Innovation Solution
The development of a vertical capacitive depletion field effect transistor (VCDFET) with interleaved gate regions and heavier-than-typical drift region doping, allowing for lower RON at a given BV, achieved through a simplified fabrication process with fewer steps, such as three masking steps, and featuring a direct current path between source and drain electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If dopant concentration in drift regions is decreased or drift region thickness is increased, then breakdown voltage (BV) increases, but on-resistance (RON) increases
Solution Approach 1:
The drift region is segmented into multiple regions with different dopant concentrations along the vertical direction. The upper drift region has lower dopant concentration for high breakdown voltage, while the lower drift region has higher dopant concentration for low on-resistance. This segmentation allows each region to optimize for its specific function, resolving the contradiction between high BV and low RON.
Solution Approach 2:
Different regions of the drift structure are assigned different dopant concentrations tailored to their specific functional requirements. The upper portion uses lighter doping for voltage blocking, while the lower portion uses heavier doping for current conduction. This local quality differentiation enables simultaneous optimization of breakdown voltage and on-resistance characteristics.
2Loss of energy
If dopant concentration in drift regions is increased or drift region thickness is decreased, then on-resistance (RON) decreases, but breakdown voltage (BV) decreases
Solution Approach 1:
The drift region is divided into upper and lower segments with different dopant concentrations. The lower segment uses higher dopant concentration to reduce on-resistance for low power dissipation, while the upper segment maintains lower concentration for adequate voltage blocking. This segmentation resolves the contradiction by distributing different doping levels to different functional zones.
Solution Approach 2:
The invention applies local quality by assigning heavier dopant concentration specifically to the lower drift region where current conduction is critical, while keeping the upper region lightly doped for voltage support. This localized doping strategy enables low on-resistance without compromising breakdown voltage.
3Reliability
If transistor fabrication complexity increases, then device characteristics improve, but cost increases and yield decreases
Solution Approach 1:
The drift regions are formed with different dopant concentrations during the preliminary epitaxial growth stage, before subsequent fabrication steps. This preliminary action establishes the desired doping profile early in the process, avoiding the need for additional complex doping steps later and reducing overall fabrication complexity while maintaining device performance.
Solution Approach 2:
The invention changes the doping parameter during epitaxial growth to create multi-region drift structures with different concentrations. By controlling dopant introduction during the epitaxial process rather than requiring separate diffusion or implantation steps, the method achieves complex doping profiles with simpler fabrication, improving both device characteristics and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The VCDFET achieves lower on-resistance for a given breakdown voltage, reduced fabrication costs, and improved frequency response characteristics while maintaining high BV, making it suitable for over-voltage and over-current protection applications.
Implementation Method 1
the gate region and the insulator region configured to deplete the drift region of charge carriers
Implementation Method 2
vertical capacitive depletion field effect transistor
Data Source
AI summary
Vertical capacitive depletion field effect transistors (VCDFETs) and methods for fabricating VCDFETs are disclosed. An example VCDFET includes one or more interleaved drift and gate regions. The gate region(s) may be configured to capacitively deplete the drift region(s) though one or more insulators that separate the gate region(s) from the drift region(s). The drift region(s) may have graded/non-uniform doping profiles. In addition, one or more ohmic and/or Schottky contacts may be configured to couple one or more source electrodes to the drift region(s).