Embedded-Multiplexer VCDL Cells for DLL Phase Matching
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Solution Overview
Problem
Existing delay locked loops (DLLs) introduce significant static errors and mismatches between feedback and output clock signals due to separate multiplexers and phase interpolators, which are unacceptable as clock speeds increase in digital systems.
Innovation Solution
A voltage controlled delay line (VCDL) with integrated multiplexer and phase interpolation functions in each cell, where the delay is controlled by current through load circuits based on control voltage, reducing external variations and mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate multiplexers and phase interpolators are used for feedback and output clock signals, then the DLL can provide delay compensation, but significant static errors and mismatches are introduced between feedback and output signals
Solution Approach 1:
The patent merges the multiplexer and phase interpolator functions into a single integrated unit that processes both feedback and output clock signals. This unified multiplexer/phase interpolator structure eliminates the mismatches between separate units by ensuring identical signal processing paths for both feedback and output signals, thereby resolving the static errors while maintaining delay compensation capability
2Device complexity
If separate multiplexers and phase interpolators are used for feedback and output, then the DLL structure is modular, but mismatches between these units are unaccounted for
Solution Approach 1:
The invention combines the previously separate multiplexer and phase interpolator into a single integrated unit. This merger maintains the modular structure of the DLL while ensuring that both feedback and output signals pass through identical signal processing circuits, thereby eliminating mismatches and improving signal consistency without sacrificing structural organization
3Ease of manufacture
If traditional DLL architecture with separate multiplexer/PI is used, then implementation is straightforward, but static error is significant between clock phases
Solution Approach 1:
The patent integrates the multiplexer and phase interpolator functions into a single unit, which maintains implementation simplicity while dramatically improving phase accuracy. The integrated design ensures that both feedback and output signals experience identical processing, eliminating the static errors that plague traditional separate-implementation architectures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated multiplexer and phase interpolation functions within each cell of the VCDL minimize static errors and mismatches, providing predictable and stable delay compensation across varying conditions, enhancing performance in high-speed digital systems.
Implementation Method 1
The amount of delay provided by each cell is based on the amount of current flowing through its load circuit(s), which is in turn based on a control voltage
Data Source
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AI summary
A voltage controlled delay line (VCDL). The VCDL (120) includes one or more cells (125). Each of the one or more cells includes two or more inputs (Va, VaX, Vb, VbX) and an output (Vout, VoutX). Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).