VCDL Control Voltage Tracking for Fast DLL Synchronization
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Solution Overview
Problem
Clock synchronization circuits, such as delay locked loops (DLLs), face challenges in rapidly achieving and maintaining synchronization under varying operating conditions, including power-saving modes, due to initial voltage settings that may not be optimal for all conditions, leading to prolonged synchronization times and inefficiencies in recovery.
Innovation Solution
A voltage control tracking circuit provides an initial control voltage to set the delay of the voltage controlled delay line (VCDL) during power-up and recovery, using a digital-to-analog converter (DAC) to track and record phase-dependent control voltages, ensuring rapid synchronization and minimizing erratic phase detector behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant VBIAS voltage is applied during initialization to set an initial delay of the VCDL, then the DLL can be initialized, but the synchronization time becomes prolonged under certain voltage, temperature, and frequency operating conditions
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal VBIAS voltage values in a lookup table before the DLL operates. When initialization is needed, the appropriate pre-determined voltage value is immediately retrieved and applied based on current operating conditions (voltage, temperature, frequency), eliminating the need for time-consuming real-time adjustments and enabling rapid synchronization across all operating conditions.
Solution Approach 2:
The patent changes the parameter approach by transitioning from a fixed constant VBIAS voltage to a variable voltage selected from multiple pre-determined values in a lookup table. This allows the system to adapt the VBIAS voltage parameter according to specific operating conditions (voltage, temperature, frequency), optimizing synchronization speed for each condition without requiring lengthy adjustment periods.
2Productivity
If the VBIAS voltage is optimized for rapid synchronization under one set of operating conditions, then synchronization speed improves, but performance deteriorates under different voltage, temperature, and frequency conditions
Solution Approach 1:
The patent achieves universality by creating a lookup table that contains pre-optimized VBIAS voltage values for multiple different operating conditions (various voltages, temperatures, and frequencies). This single data structure serves all operating scenarios, allowing the system to maintain rapid synchronization speed across diverse conditions by selecting the appropriate pre-optimized voltage value for each specific condition.
Solution Approach 2:
The patent applies parameter changes by organizing pre-optimized voltage values in a lookup table indexed by operating conditions. This allows dynamic selection of the appropriate VBIAS voltage parameter based on current voltage, temperature, and frequency conditions, enabling the system to adapt and maintain optimal synchronization performance across all operating environments rather than being fixed to one condition.
3Reliability
If process variations in semiconductor fabrication are reduced, then circuit performance becomes more consistent, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by pre-characterizing the VCDL delay characteristics across process variations during fabrication and using this information to pre-calculate optimal VBIAS voltage values that compensate for these variations. The lookup table stores these pre-computed values, allowing the circuit to achieve consistent performance across different process batches without requiring complex real-time calibration or additional manufacturing control steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables rapid synchronization and recovery of clock synchronization circuits across various operating conditions, reducing the time required to achieve a locked timing condition and minimizing delays during power-up and recovery from power-saving modes.
Implementation Method 1
a voltage controlled delay line (VCDL) 104 that receives a reference clock signal REF, and in response, generates a feedback clock signal FB having a delay relative to the REF signal that is based on a voltage magnitude of a control voltage VCTRL
Implementation Method 2
The loop filter is typically a low pass filter that filters out high-frequency noise of the CPOUT output to provide the VCTRL voltage
Implementation Method 3
using a digital-to-analog converter (DAC) to track and record phase-dependent control voltages
Data Source
AI summary
Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.