VCM Memristor Logic Gates for Stable Low-Voltage MAGIC Operation
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Solution Overview
Problem
Existing memristor-based logic systems, such as MAGIC, face challenges with input stability due to low set-to-reset voltage ratios in valence change memory (VCM) devices, limiting their ability to implement logic gates like NOR and requiring higher set voltages, which many VCM devices do not support.
Innovation Solution
The introduction of new MAGIC logic gates, including OR, NOT (NIMP), and XOR, which initialize the output memristor to a low resistance state and apply logic inputs based on set and reset voltages, ensuring input stability and functionality even with low set-to-reset voltage ratios, using valence change memory devices like Ta2O5.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the magnitude of the set voltage is increased to at least twice the magnitude of the reset voltage to prevent overwrite of inputs in MAGIC gate, then input stability is improved, but many RRAM devices exhibit low set-to-reset voltage ratio (even smaller than one) making this requirement difficult to meet
Solution Approach 1:
The patent inverts the traditional MAGIC gate approach by initializing the output memristor to high resistance state and using reset operation instead of set operation for logic computation. This inversion allows the use of smaller voltage magnitudes while maintaining input stability, making the gate compatible with RRAM devices that have low set-to-reset voltage ratios.
Solution Approach 2:
The patent changes the operational parameters of the MAGIC gate by modifying the initialization state of the output memristor from low resistance to high resistance, and by adjusting the voltage application sequence. This parameter change enables the gate to function correctly with devices that cannot provide sufficiently high set voltages.
2Adaptability or versatility
If traditional MAGIC gates are used with low set-to-reset voltage ratio devices, then device compatibility is improved, but input overwrite occurs and logic operations become unstable
Solution Approach 1:
By inverting the logic operation from set-based to reset-based computation, the patent enables compatibility with low voltage ratio devices while preventing input overwrite. The reset operation on the output memristor does not cause harmful effects on the input memristors, unlike the traditional set operation.
3Device complexity
If only NOT, NAND and NOR logic gates are implemented in crossbar, then implementation simplicity is maintained, but functional versatility is limited
Solution Approach 1:
The patent demonstrates that the inverted MAGIC gate can implement multiple logic functions (OR, AND, XOR, XNOR, NOT, NOR, NAND) using the same basic gate structure by varying the input configurations and voltage applications. This multi-functionality expands the versatility of the crossbar implementation without increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These new gates provide stable and reproducible logic operations, enabling more complex computations like half-adders, and reduce the number of cycles needed for logic operations, while being compatible with CMOS logic and VCM technologies, ensuring non-destructive operation and parallel processing capabilities.
Implementation Method 1
The memristors may be constructed using valence change memory (VCM) or may otherwise be compatible with CMOS logic.
Implementation Method 2
RRAM is a bipolar device where a set voltage is applied to switch the memristor to low resistance and a reset voltage is applied to switch the memristor to high resistance.
Data Source
AI summary
A method of using memristor aided logic (MAGIC), comprises connecting together two input and one output memristor between a bit line and a word line, each memristor having a high resistance state and a low resistance state, setting the output memristor to the low resistance state as an initiation state and then applying logic inputs to the input memristors. The output then depends on whether the logic inputs have set the output memristor to the high resistance state.


