VCO-ADC Coarse-Fine Counting With Interlocked Asynchronous Counters
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Solution Overview
Problem
Existing voltage-controlled-oscillator-based ADCs (VCO-ADCs) face challenges in achieving further improvements in performance and reducing power consumption, particularly in low-cost digital microphones, where the power consumption of the quantization circuitry is dominated by digital counting circuits.
Innovation Solution
A coarse-fine counting architecture for VCO-ADCs utilizing interlocked binary asynchronous counters, which includes a double asynchronous binary counter and samplers of ring oscillator output phases, reduces power consumption by eliminating the need for level shifters and minimizing hardware changes, while correcting metastability errors through a correction algorithm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional voltage-encoding-based circuits are used, then design is simple, but performance and power consumption are insufficient
Solution Approach 1:
The counting circuit is divided into two independent parts: a coarse counter that counts full oscillation cycles and a fine counter that counts fractional cycles using phase information from multiple ring oscillator taps. This segmentation allows each counter to be optimized independently, with the coarse counter using simple cycle counting and the fine counter using phase interpolation, thereby reducing overall power consumption while maintaining high resolution and accuracy.
Solution Approach 2:
The patent transitions from single-dimension time-based counting to two-dimensional measurement by simultaneously counting full cycles (coarse) and measuring phase fractions (fine) across multiple ring oscillator taps. This dimensional expansion enables more precise measurement with lower power consumption by distributing the counting burden across multiple parallel phase samples rather than requiring a single high-speed counter.
2Measurement precision
If high-resolution counting is implemented, then measurement precision improves, but device complexity increases
Solution Approach 1:
The counting circuit is divided into two independent parts: a coarse counter that counts full oscillation cycles and a fine counter that counts fractional cycles using phase information from multiple ring oscillator taps. This segmentation allows each counter to be optimized independently, with the coarse counter using simple cycle counting and the fine counter using phase interpolation, thereby reducing overall power consumption while maintaining high resolution and accuracy.
Solution Approach 2:
The patent introduces phase information from multiple ring oscillator taps as an intermediary to bridge the coarse cycle counting and fine fractional measurement. By sampling the phase at multiple intermediate points during each oscillation cycle, the system achieves high resolution without requiring a single complex high-speed counter, thus reducing device complexity while maintaining measurement precision.
3Use of energy by moving object
If power consumption is reduced, then energy efficiency improves, but metastability errors increase
Solution Approach 1:
The patent performs preliminary sampling of the phase at multiple ring oscillator taps before the final counting decision is made. By pre-sampling the phase information at several intermediate points during the oscillation cycle, the system prepares accurate phase data in advance, allowing the fine counter to accurately determine fractional cycles without suffering from metastability errors that would occur with single-point sampling at lower power consumption levels.
Solution Approach 2:
The system uses feedback by continuously monitoring phase information from multiple ring oscillator taps and using this information to correct and refine the counting measurement. The phase samples provide feedback that allows the fine counter to accurately determine the fractional cycle position, compensating for potential metastability issues and ensuring reliable measurements even at reduced power consumption levels.
Data Source
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AI summary
An analog-to-digital converter includes a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal; a double binary counter having a first input coupled to a first output of the VCO, a second input coupled to a second output of the VCO; a first set of registers coupled to the first output of the double binary counter; a second set of registers coupled to the second output of the double binary counter; sense amplifiers coupled to the outputs of the VCO; and a correction component coupled to the first set of registers, the second set of registers, and the sense amplifiers, wherein the correction component generates a coarse count, a fine count, and combines the coarse count and the fine count to provide a digital output signal representative of the analog input signal.