VCO-ADC Switched-Capacitor Feedback for Linearized Conversion
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Solution Overview
Problem
Classical microphone ADCs face challenges in power consumption and dynamic range, particularly in deep submicron CMOS processes, which are not fully compatible with switched-capacitor sigma-delta modulator ADCs, and are sensitive to nonlinear tuning curves and flicker noise.
Innovation Solution
A voltage-controlled oscillator (VCO) with an analog feedback loop using frequency-dependent resistors (FDRs) is implemented, which linearizes the output frequency versus input voltage characteristic and attenuates flicker noise, allowing for improved linearity and compatibility with deep submicron CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If switched-capacitor sigma-delta modulator ADCs are used in classical microphone designs, then the ADC functionality is achieved, but power consumption increases and dynamic range deteriorates
Solution Approach 1:
The patent replaces the traditional switched-capacitor sigma-delta modulator architecture with a voltage-controlled oscillator (VCO) based architecture. This substitution fundamentally changes the conversion mechanism from time-based sampling to frequency-based conversion, achieving lower power consumption and improved dynamic range by exploiting the natural resonance and oscillation characteristics of the VCO circuit rather than relying on high-speed switching operations.
Solution Approach 2:
The invention changes the operating parameters of the ADC by using a VCO whose oscillation frequency varies with input voltage. Instead of using fixed switching frequencies and capacitor values, the system modulates the oscillation frequency of the VCO in response to the input signal, allowing for continuous adjustment of conversion parameters to optimize power consumption and dynamic range across different signal levels.
2Adaptability or versatility
If deep submicron CMOS processes are used for SoC integration, then integration density improves, but compatibility with switched-capacitor sigma-delta modulator ADCs deteriorates
Solution Approach 1:
The patent replaces the switched-capacitor architecture with a VCO-based architecture that is inherently more compatible with deep submicron CMOS processes. The VCO circuit uses standard CMOS transistors and resistors to generate oscillations, avoiding the need for precise capacitor matching and high-speed switching that are difficult to implement in deep submicron technologies. This substitution enables seamless integration into System on Chip (SoC) designs while maintaining full compatibility with advanced manufacturing processes.
3Measurement precision
If VCO-based ADC is implemented, then linearity improves, but device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the output of the VCO is fed back through a frequency-dependent resistor (FDR) to the input node. This feedback loop automatically linearizes the VCO's output frequency versus input voltage characteristic by compensating for nonlinearities in real-time. The FDR creates a negative feedback path that stabilizes the operating point and reduces distortion, achieving improved linearity without requiring complex external linearization circuits or multiple VCO stages.
Solution Approach 2:
The invention changes the electrical parameters of the circuit components, particularly using a frequency-dependent resistor (FDR) whose resistance varies with the oscillation frequency. This parameter change allows the feedback network to automatically adjust its characteristics based on the operating conditions, providing linearization across a wide range of input voltages and frequencies without requiring complex control logic or multiple adjustable components.
Data Source
AI summary
An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.