VCO Buffer Topology for Parasitic Capacitance Noise Cancellation
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Solution Overview
Problem
Current PLL circuits operating at millimeter-wave frequencies face stringent integrated phase noise specifications, particularly 1/f noise, which are challenging to meet due to non-linear parasitic capacitances in voltage-controlled oscillators (VCOs) and buffer circuits.
Innovation Solution
The implementation of a buffer circuit with a second transistor coupled across the first transistor, where the gate of the first transistor is connected to the drain and source of the second transistor, and the gate of the second transistor is connected to the source of the first transistor, compensates for the non-linearity of the parasitic gate-source capacitance of the first transistor using parasitic gate-source and gate-drain capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a CML buffer is used with the VCO to maintain constant DC current, then the buffer provides stable current over PVT variations, but the parasitic gate-source capacitance of the buffer transistor introduces non-linearity that degrades phase noise performance
Solution Approach 1:
The patent converts the harmful non-linear parasitic capacitance into a beneficial linearizing effect by introducing a second transistor whose parasitic capacitances (Cgs2 and Cgd2) are positioned to cancel the non-linearity of the first transistor's parasitic capacitance (Cgs1). This transforms the previously harmful capacitance effects into a useful linearization mechanism that reduces phase noise while maintaining the stable DC current function.
Solution Approach 2:
The patent employs asymmetric coupling of the second transistor across the first transistor, with specific asymmetric connections: the gate of the first transistor connects to both drain and source of the second transistor, while the gate of the second transistor connects only to the source of the first transistor. This asymmetric configuration creates the necessary conditions for the parasitic capacitances to cancel each other's non-linear effects.
2Speed
If millimeter-wave frequencies are used for communication, then higher data rates and bandwidth are achieved, but stringent integrated phase noise specifications become difficult to meet
Solution Approach 1:
The patent changes the electrical parameters of the buffer circuit by introducing a second transistor with specific parasitic capacitance characteristics. By carefully selecting and positioning this second transistor, the overall capacitance profile of the buffer is modified to linearize the VCO control, thereby reducing phase noise at millimeter-wave frequencies and meeting the stringent specifications required for high-frequency operation.
Data Source
AI summary
A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.