VCO Activation Signal Calibration for Low-Capacitance CDR Tuning
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Solution Overview
Problem
Conventional CDR circuits with binary phase detectors face high energy consumption and low output frequency due to the use of four varactors, leading to increased parasitic capacitance and energy requirements.
Innovation Solution
A circuit arrangement using a voltage-controlled oscillator with only two varactors, controlled by a single control signal, reducing parasitic capacitance and energy consumption while increasing output frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If four varactors are used in the voltage-controlled oscillator, then the frequency tuning range is sufficient, but the parasitic capacitance increases and energy consumption rises
Solution Approach 1:
The patent extracts and removes two varactors from the conventional four-varactor VCO configuration, reducing the component count to two varactors. This extraction eliminates the associated parasitic capacitance and energy consumption while maintaining the frequency tuning functionality through an alternative control mechanism using a single control signal with calibrated activation.
2Speed
If four varactors are used in the voltage-controlled oscillator, then the frequency tuning is achievable, but the output frequency is limited due to increased parasitic capacitance
Solution Approach 1:
By removing two varactors from the configuration, the total parasitic capacitance is reduced, which directly enables higher output frequencies. The extraction principle allows the oscillator to operate at higher speeds by eliminating the capacitance bottleneck present in conventional four-varactor designs.
3Use of energy by moving object
If two digital control signals are used for frequency adjustment, then the frequency tuning is precise, but the energy consumption increases
Solution Approach 1:
The patent merges the functionality of two separate digital control signals into a single control signal. This control signal contains multiple activation levels that correspond to different frequency settings. By combining multiple control functions into one signal, the energy consumption is reduced while the frequency tuning capability is preserved through the calibrated activation levels of the remaining two varactors.
4Power
If two digital control signals are used for fine adjustment, then the frequency precision is maintained, but the current requirements increase
Solution Approach 1:
The control functionality of two digital signals is merged into a single control signal with calibrated activation levels. This single signal controls two varactors that together provide the necessary frequency adjustment range and precision. The merging reduces the total current requirements while maintaining the ability to achieve precise frequency tuning through the coordinated action of the two varactors响应于单一控制信号的不同激活电平。
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves lower current requirements and higher output frequencies, enabling a more compact layout and reduced energy consumption in CDR circuits.
Implementation Method 1
The frequency change is set by two varactor (diode)s or tuning diodes or capacitance diodes or varicaps (12, 14)
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
In order to develop a circuit arrangement (100) and also a method for calibrating at least one activation signal (Vbb) provided for a voltage-controlled oscillator (10) such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed - that the respective number of clock cycles (N) for at least one calibration oscillator (50) and at least one reference oscillator (30) associated with the calibration oscillator (50) is counted by means of at least one clock cycle counter (70) connected downstream of the calibration oscillator (50) and the reference oscillator (30) and a clock error (DE) resulting from the difference between these two numbers of clock cycles (N) is integrated and - that the clock error (DE) is converted by means of at least one digital-to-analogue converter (90) connected downstream of the clock counter (70) into analogue tuning signals (Vcm, Vcm-, Vcm+) from which the calibrated activation signal (Vbb) is derived.