VCO Quantizer Feedback for Excess Loop Delay in Delta-Sigma Converters
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Solution Overview
Problem
Continuous-time delta sigma converters face excess loop delay due to finite switching times and parasitic capacitance, which affects the stability and bandwidth of the modulator, especially when using a multiphase voltage controlled oscillator (VCO) as a quantizer, and conventional summing circuits introduce parasitic poles and increased power consumption.
Innovation Solution
A feedback loop from the output of a VCO-based quantizer to the input of the last integrator of the loop filter, incorporating a delay circuit and switched capacitor digital-to-analog converters (DACs) that differentiate the digital output signal twice, reducing excess loop delay by providing a double differentiated analog signal to the last integrator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiphase VCO based quantizer is used, then integration function is improved, but excess loop delay increases
Solution Approach 1:
The feedback path is segmented into multiple independent paths: one path goes through the VCO quantizer for integration, while another direct path bypasses the VCO to provide undelayed feedback. This segmentation allows the system to simultaneously benefit from VCO integration while compensating for its delay through the direct path.
Solution Approach 2:
A direct feedback path acts as an intermediary to compensate for the delay introduced by the VCO quantizer. This intermediary path provides a delayed version of the feedback signal that can be used to correct the excess loop delay, allowing the VCO to maintain its integration function without compromising stability.
2Ease of operation
If conventional active summing circuit is used, then summing function is improved, but bandwidth is limited by amplifier pole
Solution Approach 1:
The conventional active summing circuit using amplifiers is replaced with a passive summing approach using current steering DACs and resistive networks. This substitution eliminates the amplifier bandwidth limitation (pole) while maintaining the summing function, as passive circuits do not have the same frequency response constraints as active amplifier-based circuits.
3Speed
If low feedback resistance is used, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The feedback resistance value is optimized to a specific range that balances bandwidth and power consumption. Rather than using arbitrarily low resistance values, the patent selects feedback resistance values that achieve sufficient bandwidth while minimizing the current draw and associated power consumption in the feedback network.
4Productivity
If current steering feedback DACs are used, then conversion function is improved, but setup time requirements increase
Solution Approach 1:
The digital feedback bits are prepared and latched in advance before the clock edge that triggers the current steering DAC. This preliminary action ensures that the data is stable and ready for conversion, meeting the setup time requirements of the DAC and preventing noise degradation from timing violations.
Data Source
AI summary
A continuous-time delta sigma converter includes a loop filter having a plurality of serially coupled integrators including a first integrator responsive to an input of the Delta Sigma converter and a last integrator responsive to a first feedback loop and providing an integrated output signal, and a voltage controlled oscillator (VCO) based quantizer responsive to the loop filter for integrating the integrated output signal and providing a digital output signal. The first feedback loop includes a first time delay circuit responsive to the output of the quantizer and at least one switched capacitor digital to analog converter (DAC) responsive to the first time delay circuit. The first feedback loop is configured to differentiate the digital output signal twice and provide the last integrator of the loop filter with a double differentiated analog signal to reduce excess loop delay.