VCO Gain Calibration Using PLL and FLL for Low-Jitter Locking
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Solution Overview
Problem
Phase locked loop (PLL) circuits face challenges in achieving wide band operation with low bandwidth and high lock time, along with difficulty in reducing jitter and phase noise.
Innovation Solution
A circuit with a controllable oscillator and bias signal generator, utilizing first and second bias calibrators to calibrate the voltage and transconductance of the oscillator control signal, switching between frequency locked loop and phase locked loop modes to optimize PLL performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a charge pump circuit is employed to generate control signals for wide band PLL operation, then the PLL can operate over a wide band of frequencies, but the bandwidth becomes low and lock time becomes high
Solution Approach 1:
The calibration process is segmented into two distinct phases: voltage calibration using PLL mode and gain calibration using FLL mode. This segmentation allows each calibration step to optimize specific parameters independently, resolving the contradiction between wide frequency range operation and fast lock time by separating the calibration functions into specialized modes.
Solution Approach 2:
The patent performs preliminary voltage calibration of the VCO control signal before entering FLL mode for gain calibration. This preliminary action ensures that the VCO is properly biased before the more complex FLL calibration sequence, enabling faster overall convergence and reducing lock time while maintaining wide band operation capability.
2Adaptability or versatility
If the PLL is designed for wide band operation, then it can cover multiple frequencies, but phase noise and jitter reduction becomes difficult
Solution Approach 1:
The patent employs feedback mechanisms in both PLL and FLL modes during calibration. The PLL mode provides phase error feedback for voltage calibration, while the FLL mode provides frequency error feedback for gain calibration. This dual feedback approach enables precise control of phase noise and jitter across the wide frequency range, resolving the contradiction between frequency coverage and signal quality.
Solution Approach 2:
The calibration process dynamically changes critical parameters including VCO control voltage, bias current, and transconductance values. By adjusting these parameters through systematic calibration in both PLL and FLL modes, the system optimizes phase noise performance across the entire wide frequency range, eliminating the trade-off between frequency range and phase noise reduction.
3Loss of time
If the PLL bandwidth is increased to reduce lock time, then locking becomes faster, but phase noise increases
Solution Approach 1:
The patent implements dynamic bandwidth adjustment through two-stage calibration. During PLL voltage calibration, a wider bandwidth enables faster initial locking. During subsequent FLL gain calibration, the bandwidth is optimized for precise frequency tracking and phase noise reduction. This dynamic adaptation resolves the contradiction by allowing different bandwidth settings at different calibration stages.
Solution Approach 2:
The voltage calibration phase serves as a preliminary action that establishes optimal operating conditions before the main FLL gain calibration. This preliminary voltage optimization enables the subsequent FLL calibration to focus specifically on gain precision and phase noise reduction, achieving both fast locking and low phase noise without compromise.
Data Source
AI summary
Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.