VCO Impedance Measurement Circuit for PDN Bounce Sensing
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Solution Overview
Problem
High-performance computing (HPC) circuits face challenges with power delivery network (PDN) stability due to large current consumption, leading to power or ground bounce, signal integrity issues, and electromagnetic interference (EMI), which are exacerbated by increasing package sizes, and existing power impedance measurement (PIM) circuits face timing issues and area overhead.
Innovation Solution
An impedance measurement circuit employing a current source, voltage controlled oscillator (VCO), and delay circuits for time-domain and frequency-domain sensing, allowing for efficient and accurate estimation of power voltage drops in PDN circuits, using equivalent-time sampling (ETS) and built-in self-test (BIST) methods to measure power impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power impedance measurement circuits are added to ensure stable PDN, then measurement capability is improved, but area overhead increases
Solution Approach 1:
The patent combines the power impedance measurement function with the existing voltage controlled oscillator (VCO) circuit. The VCO serves dual purposes: generating clock signals for digital circuits and sensing power voltage for impedance measurement. This merging eliminates the need for separate measurement circuitry, reducing area overhead while maintaining measurement capability.
Solution Approach 2:
The VCO is designed to perform multiple functions simultaneously: it acts as both a clock signal generator for the digital logic and a power monitoring sensor. By making the VCO universal, the patent avoids adding dedicated measurement hardware, thus solving the area overhead problem while preserving accurate power impedance measurement functionality.
2Productivity
If trigger time and sampling time are made close for fast measurement, then measurement speed is improved, but timing issues arise in digital circuits
Solution Approach 1:
The patent introduces a delay circuit that generates a delayed sampling clock signal in advance. This delayed signal is used to trigger the sampling operation, ensuring that the sampling occurs at an appropriate time relative to the power voltage transition. By performing the timing adjustment preliminarily through the delay circuit, the system achieves both fast measurement and reliable timing without direct conflict between trigger and sampling events.
3Productivity
If HPC circuits operate at high speed with large current, then computing performance is improved, but power bounce and ground bounce increase
Solution Approach 1:
The patent implements a feedback mechanism where the VCO continuously monitors the power voltage and generates measurement data reflecting power bounce conditions. This feedback information about power quality is made available to the system, enabling detection and analysis of power delivery network issues that arise during high-performance operation.
Solution Approach 2:
The VCO serves itself by using its own operating characteristics to sense power voltage variations. The circuit monitors its own power supply conditions through the VCO's inherent voltage sensitivity, enabling self-diagnosis of power bounce issues without requiring external monitoring equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high bandwidth and timing resolution for telecommunications, reduces area and power costs, and ensures stable PDN operation by accurately measuring power impedance, thereby addressing signal integrity and EMI issues in HPC circuits.
Implementation Method 1
a voltage controlled oscillator (VCO), generating an oscillation signal according to a power voltage on the power rail
Implementation Method 2
delaying the sampling clock signal by a delayed amount to generate a delayed sampling clock signal
Data Source
AI summary
An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.