VCO Element Layout for Uniform Parasitics and Phase Matching

The patent applies asymmetry by dividing electronic elements into two subsets and arranging them in different sequences (odd order for first subset, even order for second subset). This asymmetric arrangement compensates for the mismatched parasitic resistance and capacitance caused by conventional sequential ordering, thereby reducing phase differences and frequency offsets while maintaining circuit connection simplicity.

The patent applies local quality by optimizing the arrangement of specific electronic element subsets (first subset in odd order, second subset in even order) to locally reduce parasitic resistance effects. This localized optimization ensures that conductive lines connecting adjacent elements have more uniform lengths and thus more uniform parasitic resistance, reducing phase offset and delay while maintaining signal transmission speed.

The patent applies segmentation by dividing the set of N electronic elements into two subsets (first electronic element subset and second electronic element subset). Each subset is arranged independently in a specific sequence (odd order and even order respectively), which optimizes the overall layout to reduce connection lengths and parasitic resistance while maintaining compact IC layout area.